fsl_p5020_ds.rar

/* sysLib.c - Freescale P5020DS board system-dependent library */ /* * Copyright (c) 2011-2013, 2015 Wind River Systems, Inc. * * The right to copy, distribute, modify or otherwise make use * of this software may be licensed only pursuant to the terms * of an applicable Wind River license agreement. */ /* modification history -------------------- 21apr15,wyt Remove interrupt lock before the cpcInvoke(). (VXW6-84305) 01x,22feb13,d_l fixed time base enable issue on non-zero CPUs. (WIND00403567) 01w,26nov12,j_z fix SRIO share memory End parameter error. (WIND00395925) 01v,20oct12,j_z added support for SRIO. 01u,09apr12,h_k fixed reboot failure on non-primary Core0 in AMP. (WIND00344093) allowed to disable L3 cache only on Core0. (WIND00341977) removed RESERVED_ATOMICS. added missing L2 cache flush on non-primary core in SMP at reboot. (WIND00341662) 01t,05mar12,y_y add vxBus I2C support. 01s,29feb12,y_y remove the MAX_CPUS, superceded by PHYS_MAX_CPUS for P3041 SMP M2N support. (WIND00335350) 01r,28feb12,agf resolving merge conflicts 0lq,15feb12,x_s WIND00247656: added comments in function sysCpuEnable(). 01p,07feb12,x_s WIND00331187: added Errata A-003999(FPU) implementation. 01o,01feb12,y_y add TM_ANCHOR_ADRS mapping in sysPhysMemDesc[]. 01n,01feb12,y_y modified the AMP core1-X reboot in sysToMonitor(). 01m,01feb12,agf WIND00329621: Remove SYSTEM_GLOBALS, superceded by RESERVED_ATOMICS 01l,11nov11,ers WIND00297094: cache fix for vmPageLock/Unlock. WIND00309426: Moved L1 parity handling to arch. 01k,26oct11,y_y modified SYS_MODEL to meet the BSPVTS test and freescale P3041 board. 01j,26oct11,y_y modified the coreShow() routine and misc code clean. 01i,01oct11,ers Replaced DYNAMIC_WRLOAD with generic wrload and removed unreferenced SERDES errata workaround code. 01h,31aug11,y_y modified the sysClkFreqGet() and misc code clean up. 01g,14aug11,y_y added I2C device support. 01f,04aug11,y_y add SPI device support and misc code clean up. 01e,04jul11,b_m change ppc timebase and SDHC clock frequency. 01d,22jun11,b_m ensure MII-1 bus is enabled in FPGA. 01c,15jun11,b_m fixed the dtsec mdio mux logic in sysMux1Ctrl(). 01b,10jun11,y_y updated clock frequencies caculation for real hardware. 01a,05mar11,syt adapted from fsl_p4080_ds, version 03e. */ /* DESCRIPTION This library provides board-specific routines for p5020ds. The chip drivers included are: sysCacheErrorLib.c - cache error handler install code. sysCache.c - L2/L3 cache support. usbPciStub.c - USB Host/Device controller support. INCLUDE FILES: sysLib.h SEE ALSO: \tb VxWorks Programmer's Guide: Configuration */ /* includes */ #include <vxWorks.h> #include <vsbConfig.h> #include <vme.h> #include <memLib.h> #include <cacheLib.h> #include <sysLib.h> #include "config.h" #include <string.h> #include <intLib.h> #include <logLib.h> #include <stdio.h> #include <taskLib.h> #include <vxLib.h> #include <tyLib.h> #include <arch/ppc/mmuE500Lib.h> #include <arch/ppc/vxPpcLib.h> #include <private/vmLibP.h> #include <miiLib.h> #include <cpuset.h> #ifdef INCLUDE_WRLOAD # include <wrload.h> IMPORT UINT32 usrWrloadBiasHighGet(WRLOAD_ID id); /* from usrWrload.c */ IMPORT UINT32 usrWrloadBiasLowGet (WRLOAD_ID id); /* from usrWrload.c */ #endif /* INCLUDE_WRLOAD */ #ifdef _WRS_CONFIG_SMP # include <private/cpcLibP.h> # include <private/kernelLibP.h> /* KERNEL_ENTERED_ME() */ #endif /* _WRS_CONFIG_SMP */ #ifdef INCLUDE_AMP # include <vxIpiLib.h> #endif /* INCLUDE_AMP */ #ifdef INCLUDE_P5020_FMAN_UCODE # include <hwif/vxbus/hwConf.h> # include <h/vxbus/vxbAccess.h> #endif /* INCLUDE_P5020_FMAN_UCODE */ #ifdef DRV_RESOURCE_QORIQRMAN # include <hwif/util/vxbMsgSupport.h> # include <resource/vxbQorIQRman.h> #endif /* DRV_RESOURCE_QORIQRMAN */ #ifdef DRV_SRIO_FSL IMPORT STATUS fslRioUsrIntGen (int, int, int); #endif /* DRV_SRIO_FSL */ #ifdef INCLUDE_SM_NET IMPORT void smUtilIntRoutine (void); #endif /* INCLUDE_SM_NET */ #ifdef INCLUDE_PCI_BUS # include <drv/pci/pciConfigLib.h> # include <drv/pci/pciIntLib.h> #endif /* INCLUDE_PCI_BUS */ /* globals */ char sysHwErrorString[200]; /* about 180 characters if all errors print */ #define hwErrStringEnd (&(sysHwErrorString[strlen(sysHwErrorString)])) #define hwErrStringSz (sizeof(sysHwErrorString) - strlen(sysHwErrorString) -1) /* definitions for core cluster ID setting in PIR */ #define PIR_CORE_CLUSTER_ID_SHIFT 5 #define PIR_CORE_CLUSTER_ID_MASK 0x1f #define PIR_CORE_CLUSTER_ID_SET(id) \ ((id & PIR_CORE_CLUSTER_ID_MASK) << PIR_CORE_CLUSTER_ID_SHIFT) /* protect all TLB1 entries if in a Linux-VxWorks system. */ #define PROTECTED 0 #ifdef WRLOAD_IMAGE_BUILD_PHYS_BIAS #define PHYS_BIAS_LO (UINT32) (WRLOAD_IMAGE_BUILD_PHYS_BIAS) #define PHYS_BIAS_HI (UINT32) ((UINT64)WRLOAD_IMAGE_BUILD_PHYS_BIAS >> 32) #else #define WRLOAD_IMAGE_BUILD_PHYS_BIAS 0 #define PHYS_BIAS_LO 0 #define PHYS_BIAS_HI 0 #endif #ifdef INCLUDE_WRLOAD_IMAGE_BUILD /* * WARNING: The loaded image base address (LOCAL_MEM_LOCAL_ADRS + * WRLOAD_IMAGE_BUILD_PHYS_BIAS) must be modulo RAM_TLB_SZ size. */ #define RAM_TLB_SZ ( (LOCAL_MEM_SIZE <= 0x04000000) ? _MMU_TLB_SZ_64M \ : (LOCAL_MEM_SIZE <= 0x10000000) ? _MMU_TLB_SZ_256M \ : (LOCAL_MEM_SIZE <= 0x40000000) ? _MMU_TLB_SZ_1G : -1) #if (LOCAL_MEM_SIZE > 0x80000000) #error Additional TLB entries will need to be added to sysStaticTlbDesc[]. #endif #if ((LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE + WRLOAD_IMAGE_BUILD_PHYS_BIAS) \ > PHYS_MEM_SIZE) #error Your image footprint exceeds available memory. #endif #endif /* INCLUDE_WRLOAD_IMAGE_BUILD */ TLB_ENTRY_DESC sysStaticTlbDesc [] = { /* effAddr, Unused, realAddr, ts | size | attributes | permissions */ /* TLB #0. Flash */ /* needed be first entry here */ { FLASH_BASE_ADRS, 0x0, FLASH_BASE_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_X }, /* * The RAM execution area must be the 2nd entry because romInit uses the 2nd * TLB for this area. When this TLB is written it replaces the romInit one. * You can't overlap TLBs. You must have a TLB to use an area. */ #ifdef INCLUDE_WRLOAD_IMAGE_BUILD { LOCAL_MEM_LOCAL_ADRS, PHYS_BIAS_HI, LOCAL_MEM_LOCAL_ADRS + PHYS_BIAS_LO, _MMU_TLB_TS_0 | RAM_TLB_SZ | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | CAM_DRAM_CACHE_MODE | _MMU_TLB_ATTR_M | _MMU_TLB_PERM_X }, #else { LOCAL_MEM_LOCAL_ADRS, LOCAL_MEM_ERPN, LOCAL_MEM_LOCAL_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_1G | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | CAM_DRAM_CACHE_MODE | _MMU_TLB_ATTR_M | _MMU_TLB_PERM_X }, #endif /* INCLUDE_WRLOAD_IMAGE_BUILD */ /* WR Hypervisor expects this area in the 3rd TLB entry */ { CCSBAR, 0x0, CCSBAR, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, #if (LOCAL_MEM_SIZE > 0x40000000) { LOCAL_MEM_LOCAL_ADRS + 0x40000000, LOCAL_MEM_ERPN, LOCAL_MEM_LOCAL_ADRS + 0x40000000, _MMU_TLB_TS_0 | _MMU_TLB_SZ_1G | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_M | _MMU_TLB_PERM_X }, #endif /* (LOCAL_MEM_SIZE > 0x40000000) */ #ifdef INCLUDE_VIRTUAL_SM { VIRTUAL_SM_BASE, 0, VIRTUAL_SM_BASE_PHYS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_M| _MMU_TLB_PERM_X }, #endif /* INCLUDE_VIRTUAL_SM */ { PIXIS_BASE, 0x0, PIXIS