fsl_t1040_qds.rar

/* sysLib.c - Freescale T1040QDS board system-dependent library */ /* * Copyright (c) 2014-2016 Wind River Systems, Inc. * * The right to copy, distribute, modify or otherwise make use * of this software may be licensed only pursuant to the terms * of an applicable Wind River license agreement. */ /* modification history -------------------- 04nov16,syt Enable the slave core's L2 cache sysCpuInit(). (VXW6-85765) 21apr15,wyt Remove interrupt lock before the cpcInvoke(). (VXW6-84305) 03jul14,xms initial creation. */ /* DESCRIPTION This library provides board-specific routines for t1040qds. INCLUDE FILES: sysLib.h SEE ALSO: \tb VxWorks Programmer's Guide: Configuration */ /* includes */ #include <vxWorks.h> #include <vsbConfig.h> #include <vme.h> #include <memLib.h> #include <cacheLib.h> #include <sysLib.h> #include "config.h" #include <string.h> #include <intLib.h> #include <logLib.h> #include <stdio.h> #include <taskLib.h> #include <vxLib.h> #include <tyLib.h> #include <arch/ppc/mmuE500Lib.h> #include <arch/ppc/vxPpcLib.h> #include <private/vmLibP.h> #include <miiLib.h> #include <cpuset.h> #ifdef _WRS_CONFIG_SMP # include <private/cpcLibP.h> # include <private/kernelLibP.h> /* KERNEL_ENTERED_ME() */ #endif /* _WRS_CONFIG_SMP */ #ifdef INCLUDE_T1040_FMAN_UCODE # include <hwif/vxbus/hwConf.h> # include <h/vxbus/vxbAccess.h> #endif /* INCLUDE_T1040_FMAN_UCODE */ #ifdef INCLUDE_PCI_BUS # include <drv/pci/pciConfigLib.h> # include <drv/pci/pciIntLib.h> #endif /* INCLUDE_PCI_BUS */ /* globals */ UINT32 ppcE500ICACHE_LINE_NUM = (64 * 12); UINT32 ppcE500DCACHE_LINE_NUM = (64 * 12); UINT32 ppcE500CACHE_ALIGN_SIZE = 64; /* protect all TLB1 entries if in a Linux-VxWorks system. */ #define PROTECTED 0 #define RAM_TLB_SZ _MMU_TLB_SZ_1G # define PHYS_BIAS_HI_LO 0 # define PHYS_BIAS_LO 0 # define PHYS_BIAS_HI 0 TLB_ENTRY_DESC sysStaticTlbDesc [] = { /* effAddr, Unused, realAddr, ts | size | attributes | permissions */ /* TLB #0. Flash */ /* needed be first entry here */ { FLASH_BASE_ADRS, 0x0, FLASH_BASE_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_X }, /* * The RAM execution area must be the 2nd entry because romInit uses the 2nd * TLB for this area. When this TLB is written it replaces the romInit one. * You can't overlap TLBs. You must have a TLB to use an area. */ { LOCAL_MEM_LOCAL_ADRS, _LOCAL_MEM_ERPN, LOCAL_MEM_LOCAL_ADRS, _MMU_TLB_TS_0 | RAM_TLB_SZ | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | CAM_DRAM_CACHE_MODE | _MMU_TLB_ATTR_M | _MMU_TLB_PERM_X }, { CCSBAR, 0x0, CCSBAR, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, #if (LOCAL_MEM_SIZE > 0x40000000) { LOCAL_MEM_LOCAL_ADRS + 0x40000000, _LOCAL_MEM_ERPN, LOCAL_MEM_LOCAL_ADRS + 0x40000000, _MMU_TLB_TS_0 | _MMU_TLB_SZ_1G | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_M | _MMU_TLB_PERM_X }, #endif /* (LOCAL_MEM_SIZE > 0x40000000) */ #ifdef INCLUDE_VIRTUAL_SM { VIRTUAL_SM_BASE, 0, VIRTUAL_SM_BASE_PHYS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_M| _MMU_TLB_PERM_X }, #endif /* INCLUDE_VIRTUAL_SM */ { QIXIS_BASE, 0x0, QIXIS_BASE, _MMU_TLB_TS_0 | _MMU_TLB_SZ_4K | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W | _MMU_TLB_IPROT }, { CCSBAR, 0x0, CCSBAR, _MMU_TLB_TS_1 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G } /* All these are not protected */ #ifdef DRV_RESOURCE_QORIQBMAN , { BMAN_LAW_BASE, 0x0, BMAN_LAW_BASE, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | PROTECTED | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_M }, { (BMAN_LAW_BASE + 0x01000000), 0x0, (BMAN_LAW_BASE + 0x01000000), _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | PROTECTED | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G } #endif /* DRV_RESOURCE_QORIQBMAN */ #ifdef DRV_RESOURCE_QORIQQMAN , { QMAN_LAW_BASE, 0x0, QMAN_LAW_BASE, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | PROTECTED | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_M }, { (QMAN_LAW_BASE + 0x01000000), 0x0, (QMAN_LAW_BASE + 0x01000000), _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | PROTECTED | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G } #endif /* DRV_RESOURCE_QORIQQMAN */ #ifdef INCLUDE_PCI_BUS , { PCIEX1_LAW_BASE, 0x0, PCIEX1_LAW_BASE, _MMU_TLB_TS_0 | PCI_MMU_TLB_SZ | PROTECTED | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G } , { PCIEX2_LAW_BASE, 0x0, PCIEX2_LAW_BASE, _MMU_TLB_TS_0 | PCI_MMU_TLB_SZ | PROTECTED | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G } , { PCIEX3_LAW_BASE, 0x0, PCIEX3_LAW_BASE, _MMU_TLB_TS_0 | PCI_MMU_TLB_SZ | PROTECTED | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G } , { PCIEX4_LAW_BASE, 0x0, PCIEX4_LAW_BASE, _MMU_TLB_TS_0 | PCI_MMU_TLB_SZ | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W } #endif /* INCLUDE_PCI_BUS */ , { DCSR_LAW_BASE, 0x0, DCSR_LAW_BASE, _MMU_TLB_TS_0 | _MMU_TLB_SZ_4M | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W } #if (defined (_WRS_CONFIG_SMP) || defined (INCLUDE_AMP)) && \ (LOCAL_MEM_ERPN || \ ((RAM_TLB_SZ == _MMU_TLB_SZ_64M) && \ (CPUn_SPACE_START_ADDR < \ (LOCAL_MEM_LOCAL_ADRS & 0xFC000000))) || \ ((RAM_TLB_SZ == _MMU_TLB_SZ_128M) && \ (CPUn_SPACE_START_ADDR < \ (LOCAL_MEM_LOCAL_ADRS & 0xF8000000))) || \ ((RAM_TLB_SZ == _MMU_TLB_SZ_256M) && \ (CPUn_SPACE_START_ADDR < \ (LOCAL_MEM_LOCAL_ADRS & 0xF0000000))) || \ ((RAM_TLB_SZ == _MMU_TLB_SZ_512M) && \ (CPUn_SPACE_START_ADDR < \ (LOCAL_MEM_LOCAL_ADRS & 0xE0000000))) || \ ((RAM_TLB_SZ == _MMU_TLB_SZ_1G) && \ (CPUn_SPACE_START_ADDR < (LOCAL_MEM_LOCAL_ADRS & 0xC0000000)))) /* For CPUn_SPACE to allow ISR call to sysToMonitor(): */ , { ROUND_DOWN (CPUn_SPACE_START_ADDR, 0x10000), 0, ROUND_DOWN (CPUn_SPACE_START_ADDR, 0x10000), _MMU_TLB_TS_0 | _MMU_TLB_SZ_64K | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | CAM_DRAM_CACHE_MODE | _MMU_TLB_ATTR_M } #endif /* (_WRS_CONFIG_SMP || INCLUDE_AMP) && * (_LOCAL_MEM_ERPN || (RAM_TLB_SZ == _MMU_TLB_SZ_XX) && * (CPUn_SPACE_START_ADDR < * ROUND_DOWN(LOCAL_MEM_LOCAL_ADRS, 0xXX000000))) */ }; /* * Warning, if sysStaticTlbDesc uses too many entries, mmuOptimize() may * fail to add a static entry for the sysPhysMemDesc table. */ int sysStaticTlbDescNumEnt = NELEMENTS (sysStaticTlbDesc); /* macro to compose 64-bit PHYS_ADDRs */ #define PHYS_64BIT_ADDR(h, l) (((PHYS_ADDR)(h) << 32) + (l)) /* * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array * used by the MMU to translate addresses with single page (4k) granularity. * PTE memory space should not, in general, overlap BAT memory space but * may be allowed if only Data or Instruction access is mapped via BAT. * * Address translations for local RAM, memory mapped PCI bus, the Board Control * and Status registers, the T1040 Internal Memory Map, and local FLASH RAM are * set here. * * PTEs are held in a Page Table. Page Table sizes are * integer powers of two based on amount of memory to be mapped and a * minimum size of 64 kbytes. The MINIMU