fsl_p1021_mds.rar

/* sysLib.c - Freescale p1021MDS board system-dependent library */ /* * Copyright (c) 2010-2012, 2015 Wind River Systems, Inc. * * The right to copy, distribute, modify or otherwise make use * of this software may be licensed only pursuant to the terms * of an applicable Wind River license agreement. */ /* modification history -------------------- 21apr15,wyt Remove interrupt lock before the cpcInvoke(). (VXW6-84305) 01g,12nov12,x_s Fix the AMP device filter. (WIND00387606) 01f,05mar12,y_y add vxBus I2C support. 01e,04jan12,agf Correct value used to init L2CTL register (WIND00325436) 01d,19dec11,agf Moved L1 parity handling to arch lib. (WIND00309426) 01c,14may11,y_y rewrited the I2C RTC driver.(WIND00275906) 01b,08apr11,y_y corrected typo.(WIND00266174) 01a,23nov10,y_y derived from version 01b of fsl_p2020_rdb/sysLib.c */ /* DESCRIPTION This library provides board-specific routines. The chip drivers included are: sysFslSpi.c - Freescale SPI controller support. sysSpiFlash.c - S25FL128P SPI flash driver. sysL2Cache.c - L2 cache support. usbPciStub.c - USB Host/Device controller support. INCLUDE FILES: sysLib.h SEE ALSO: \tb VxWorks Programmer's Guide: Configuration */ /* includes */ #include <vxWorks.h> #include <memLib.h> #include <cacheLib.h> #include <sysLib.h> #include "config.h" #include <string.h> #include <intLib.h> #include <stdio.h> #include <taskLib.h> #include <vxLib.h> #include <arch/ppc/mmuE500Lib.h> #include <arch/ppc/vxPpcLib.h> #include <private/vmLibP.h> #include <hwif/vxbus/vxBus.h> #ifdef _WRS_CONFIG_SMP # include <private/cpcLibP.h> # include <private/kernelLibP.h> /* KERNEL_ENTERED_ME() */ #endif /* _WRS_CONFIG_SMP */ #ifdef INCLUDE_PCI_BUS # include <drv/pci/pciConfigLib.h> # include <drv/pci/pciIntLib.h> # include "mot85xxPci.h" #endif /* INCLUDE_PCI_BUS */ #ifdef INCLUDE_SPE # include <speLib.h> #endif /* INCLUDE_SPE */ #include "p1021mds.h" /* globals */ TLB_ENTRY_DESC sysStaticTlbDesc [] = { /* effAddr, Unused, realAddr, ts | size | attributes | permissions */ { NAND_BUFFER_BASE, 0x0, NAND_BUFFER_BASE, _MMU_TLB_TS_0 | _MMU_TLB_SZ_1M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, { DDR_PHY_ADDR, 0x0, DDR_PHY_ADDR, _MMU_TLB_TS_0 | _MMU_TLB_SZ_256M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_M }, { DDR_PHY_SIZE/2, 0x0, DDR_PHY_SIZE/2, _MMU_TLB_TS_0 | _MMU_TLB_SZ_256M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_M }, { CCSBAR, 0x0, CCSBAR, _MMU_TLB_TS_0 | _MMU_TLB_SZ_1M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, #ifdef INCLUDE_L2_SRAM { L2SRAM_ADDR, 0x0, L2SRAM_ADDR, _MMU_TLB_TS_0 | _MMU_TLB_SZ_256K | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, #endif /* INCLUDE_L2_SRAM */ { BCSR_BASE_ADRS, 0x0, BCSR_BASE_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16K | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, #ifdef INCLUDE_PCI_BUS { PCIEX2_MEM_ADRS, 0x0, PCIEX2_MEM_ADRS, _MMU_TLB_TS_0 | PCI_MMU_TLB_SZ | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W }, { PCIEX1_MEM_ADRS, 0x0, PCIEX1_MEM_ADRS, _MMU_TLB_TS_0 | PCI_MMU_TLB_SZ | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W }, #endif /* INCLUDE_PCI_BUS */ }; int sysStaticTlbDescNumEnt = NELEMENTS (sysStaticTlbDesc); /* macro to compose 64-bit PHYS_ADDRs */ #define PHYS_64BIT_ADDR(h, l) (((PHYS_ADDR)(h) << 32) + (l)) /* * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array * used by the MMU to translate addresses with single page (4k) granularity. * * PTEs are held, strangely enough, in a Page Table. Page Table sizes are * integer powers of two based on amount of memory to be mapped and a * minimum size of 64 kbytes. The MINIMUM recommended Page Table sizes * for 32-bit PowerPCs are: * * Total mapped memory Page Table size * ------------------- --------------- * 8 Meg 64 K * 16 Meg 128 K * 32 Meg 256 K * 64 Meg 512 K * 128 Meg 1 Meg * . . * . . * . . * * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments] * */ PHYS_MEM_DESC sysPhysMemDesc [] = { { (VIRT_ADDR) DDR_PHY_ADDR, (PHYS_ADDR) DDR_PHY_ADDR, DDR_PHY_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \ VM_STATE_MASK_MEM_COHERENCY, VM_STATE_VALID | VM_STATE_WRITABLE | TLB_CACHE_MODE | \ VM_STATE_MEM_COHERENCY }, #ifdef INCLUDE_L2_SRAM { (VIRT_ADDR) L2SRAM_ADDR, (PHYS_ADDR) L2SRAM_ADDR, L2SRAM_WINDOW_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \ VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | \ VM_STATE_GUARDED }, #endif /* INCLUDE_L2_SRAM */ { (VIRT_ADDR) NAND_BUFFER_BASE, (VIRT_ADDR) NAND_BUFFER_BASE, 0x100000, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \ VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | \ VM_STATE_GUARDED }, /* BPTR & NAND */ { (VIRT_ADDR) CCSBAR, (PHYS_ADDR) CCSBAR, CCSBAR_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \ VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | \ VM_STATE_GUARDED }, { (VIRT_ADDR) BCSR_BASE_ADRS, (PHYS_ADDR) BCSR_BASE_ADRS, 0x4000, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \ VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | \ VM_STATE_GUARDED }, #ifdef INCLUDE_PCI_BUS { (VIRT_ADDR) PCIEX1_MEM_ADRS, (PHYS_ADDR) PCIEX1_MEM_ADRS, PCIEX1_MEM_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \ VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | \ VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX1_MEMIO_ADRS, (PHYS_ADDR) PCIEX1_MEMIO_ADRS, PCIEX1_MEMIO_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \ VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | \ VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX1_IO_ADRS, (PHYS_ADDR) PCIEX1_IO_ADRS, PCIEX1_IO_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \ VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | \ VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX2_MEM_ADRS, (PHYS_ADDR) PCIEX2_MEM_ADRS, PCIEX2_MEM_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX2_MEMIO_ADRS, (PHYS_ADDR) PCIEX2_MEMIO_ADRS, PCIEX2_MEMIO_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX2_IO_ADRS, (PHYS_ADDR) PCIEX2_IO_ADRS, PCIEX2_IO_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, #endif /* INC