fsl_p1010_rdb.rar

/* sysLib.c - Freescale P1010RDB board system-dependent library */ /* * Copyright (c) 2011-2015 Wind River Systems, Inc. * * The right to copy, distribute, modify or otherwise make use * of this software may be licensed only pursuant to the terms * of an applicable Wind River license agreement. */ /* modification history -------------------- 04Feb15,h_ma add sysUsb2Enable/sysUsb2Disable enable GPIO for USB2 on fsl_p1010_rdb PB board. 02feb15,xms fix newtork issue due to MAC address fetch failure.(VXW6-84059) 31dec14,e_d add storage feature support. 15dev14,xms add P1010RDB-PB board support. 01d,29oct13,ywu add vxBus NAND flash support and fix WIND00437835. 01c,05mar12,y_y add vxBus I2C support. 01b,04jan12,agf Correct value used to init L2CTL register (WIND00325436) 01a,10sep11,fao derived from fsl_p1020_rdb/sysLib.c */ /* DESCRIPTION This library provides board-specific routines for P1010RDB INCLUDE FILES: SEE ALSO: \tb VxWorks Programmer's Guide: Configuration */ /* DESCRIPTION This library provides board-specific routines. The chip drivers included are: flashMem.c - S29GL128P flash driver for NVRam. sysMtd.c - S29GL128P flash driver for tureFFS. sysFslSpi.c - FreeScale SPI controller support. spS25flxxSpiFlash.c - S25FL128P SPI flash driver. sysL2Cache.c - L1 cache parity support. sysGpio.c - GPIO controller driver. usbPciStub.c - USB Host/Device controller support. INCLUDE FILES: sysLib.h SEE ALSO: \tb VxWorks Programmer's Guide: Configuration */ /* includes */ #include <vxWorks.h> #include <memLib.h> #include <cacheLib.h> #include <sysLib.h> #include "config.h" #include <string.h> #include <intLib.h> #include <logLib.h> #include <stdio.h> #include <taskLib.h> #include <vxLib.h> #include <tyLib.h> #include <arch/ppc/mmuE500Lib.h> #include <arch/ppc/vxPpcLib.h> #include <private/vmLibP.h> #include <miiLib.h> #include <hwif/vxbus/vxBus.h> #ifdef INCLUDE_PCI_BUS # include <drv/pci/pciConfigLib.h> # include <drv/pci/pciIntLib.h> #endif /* INCLUDE_PCI_BUS */ #ifdef INCLUDE_SPE # include <speLib.h> #endif /* INCLUDE_SPE */ /* globals */ TLB_ENTRY_DESC sysStaticTlbDesc [] = { /* effAddr, Unused, realAddr, ts | size | attributes | permissions */ /* TLB #0. Flash */ /* needed be first entry here */ { FLASH_BASE_ADRS, 0x0, FLASH_BASE_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, { (FLASH_BASE_ADRS + 0x1000000), 0x0, (FLASH_BASE_ADRS + 0x1000000), _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, { 0x00000000, 0x0, 0x00000000, _MMU_TLB_TS_0 | _MMU_TLB_SZ_1G | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | CAM_DRAM_CACHE_MODE | _MMU_TLB_IPROT | _MMU_TLB_ATTR_M }, { CCSBAR, 0x0, CCSBAR, _MMU_TLB_TS_0 | _MMU_TLB_SZ_1M | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W | _MMU_TLB_IPROT }, #ifdef INCLUDE_PCI_BUS { PCIEX2_MEM_ADRS, 0x0, PCIEX2_MEM_ADRS, _MMU_TLB_TS_0 | PCI_MMU_TLB_SZ | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W }, #endif /* INCLUDE_PCI_BUS */ #ifdef INCLUDE_NAND_FLASH { NAND_BUFFER_BASE, 0x0, NAND_BUFFER_BASE, _MMU_TLB_TS_0 | _MMU_TLB_SZ_1M | _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G }, #endif /* INCLUDE_NAND_FLASH */ }; int sysStaticTlbDescNumEnt = NELEMENTS (sysStaticTlbDesc); /* macro to compose 64-bit PHYS_ADDRs */ #define PHYS_64BIT_ADDR(h, l) (((PHYS_ADDR)(h) << 32) + (l)) /* * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array * used by the MMU to translate addresses with single page (4k) granularity. * PTE memory space should not, in general, overlap BAT memory space but * may be allowed if only Data or Instruction access is mapped via BAT. * * PTEs are held, strangely enough, in a Page Table. Page Table sizes are * integer powers of two based on amount of memory to be mapped and a * minimum size of 64 kbytes. The MINIMUM recommended Page Table sizes * for 32-bit PowerPCs are: * * Total mapped memory Page Table size * ------------------- --------------- * 8 Meg 64 K * 16 Meg 128 K * 32 Meg 256 K * 64 Meg 512 K * 128 Meg 1 Meg * . . * . . * . . * * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments] * */ PHYS_MEM_DESC sysPhysMemDesc [] = { { (VIRT_ADDR) PHYS_MEM_START, (PHYS_ADDR) PHYS_MEM_START, PHYS_MEM_SIZE, MMU_ATTR_VALID_MSK | MMU_ATTR_PROT_MSK | MMU_ATTR_CACHE_MSK, MMU_ATTR_VALID | MMU_ATTR_SUP_RWX | TLB_CACHE_MODE | MMU_ATTR_CACHE_COHERENCY }, { (VIRT_ADDR) CCSBAR, (PHYS_ADDR) CCSBAR, CCSR_SIZE, MMU_ATTR_VALID_MSK | MMU_ATTR_PROT_MSK | MMU_ATTR_CACHE_MSK, MMU_ATTR_VALID | MMU_ATTR_SUP_RWX | MMU_ATTR_CACHE_OFF | MMU_ATTR_CACHE_COHERENCY | MMU_ATTR_CACHE_GUARDED }, #ifdef INCLUDE_PCI_BUS { (VIRT_ADDR) PCIEX1_MEM_ADRS, (PHYS_ADDR) PCIEX1_MEM_ADRS, PCIEX1_MEM_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX1_MEMIO_ADRS, (PHYS_ADDR) PCIEX1_MEMIO_ADRS, PCIEX1_MEMIO_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX1_IO_ADRS, (PHYS_ADDR) PCIEX1_IO_ADRS, PCIEX1_IO_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX2_MEM_ADRS, (PHYS_ADDR) PCIEX2_MEM_ADRS, PCIEX2_MEM_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX2_MEMIO_ADRS, (PHYS_ADDR) PCIEX2_MEMIO_ADRS, PCIEX2_MEMIO_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, { (VIRT_ADDR) PCIEX2_IO_ADRS, (PHYS_ADDR) PCIEX2_IO_ADRS, PCIEX2_IO_SIZE, VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED, VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED }, #endif /* INCLUDE_PCI_BUS */ { (VIRT_ADDR) FLASH_BASE_ADRS, (PHYS_ADDR) FLASH_BASE_ADRS, FLASH_SIZE, MMU_ATTR_VALID_MSK | MMU_ATTR_PROT_MSK | MMU_ATTR_CACHE_MSK, MMU_ATTR_VALID | MMU_ATTR_SUP_RWX | MMU_ATTR_CACHE_OFF | MMU_ATTR_CACHE_COHERENCY | MMU_ATTR_CACHE_GUARDED }, #ifdef INCLUDE_NAND_FLASH { (VIRT_ADDR) NAND_BUFFER_BASE, (VIRT_ADDR) NAND_BUFFER_BASE, NAND_BUFFER_SIZE, MMU_ATTR_VALID_MSK | MMU_ATTR_PROT_MSK | MMU_ATTR_CACHE_MSK, MMU_ATTR_VALID | MMU_ATTR_SUP_RWX | MMU_ATTR_CACHE_OFF | MMU_ATTR_CACHE_GUARDED }, #endif /* INCLUDE_NAND_FLASH */ }; int sysPhysMemDescNumEnt = NELEMENTS(sysPhysMemDesc); int sysBus = BUS_TYPE_NONE; /* system bus type */ int sysCpu = CPU; /* system CPU type */ char * sysBootLine = BOOT_LINE_ADRS; /* address of boot l