Synthesis www.xilinx.com 2
UG901 (v2016.2) June 8, 2016
Revision History
The following table shows the revision history for this document:
Date Version Revision History
06/03/216 2016.2 Added DIRECT_RESET XDC Example in Chapter 2.
Added DIRECT_ENABLE XDC Example in Chapter 2.
04/06/2016 2016.1 Clarified Creating Run Strategies in Chapter 1.
Added Creating a New Strategy in Chapter 1.
Changed control_set_opt_threshold in Using Synthesis in Chapter 1
Added -retiming to Using Synthesis in Chapter 1
Added -max_uram, -max_bram_cascade_height, -max_uram_cascade_height,
-assert and -no_srlextract to Using Synthesis, Running Synthesis with Tcl, and
Vivado Preconfigured Strategies in Chapter 1
Modified Multi-Threading in RTL Synthesis in Chapter 1
Changed Figure 1-2 diagram to match the release.
Removed “s” from Register option.
Added an additional option for Creating Run Strategies in Chapter 1.
Replaced the following figures in Chapter 1 to match the release:
Figure 1-5,Figure 1-6, Figure 1-11, Figure 1-12.
Updated KEEP_HIERARCHY Example (VHDL) in Chapter 2
Modified ASYNC_REG in Chapter 2.
Modified DONT_TOUCH in Chapter 2 to show only yes.
Modified the recommendation for MARK_DEBUG in Chapter 2.
Added EXTRACT_ENABLE in Chapter 2and EXTRACT_RESET in Chapter 2.
Changed “enable” to “reset” in EXTRACT_RESET in Chapter 2.
Added to Custom Attribute Support in Vivado in Chapter 2.
In RAM_STYLE in Chapter 2: removed extra word, “accepted” from verbiage.
Also added the ULTRA option, that it is set on a RAM or a hierarchy, and that
sub-levels of hierarchy are not affected.
In SRL_STYLE in Chapter 2, added additional -directives, and modified the
Caution.
Modified FSM_SAFE_STATE in Chapter 2.
Modified USE_DSP48 in Chapter 2.
Added an XDC example of FSM_SAFE_STATE.
added Using Synthesis Attributes in XDC files in Chapter 2.
Added True Dual-Port Asymmetric RAM Write First (Verilog) in Chapter 3.
Added UltraRAM Coding Templates in Chapter 3.
Modified Black Boxes in Chapter 3.
Modified Tristates in Chapter 3.
Changed description in Advantages of SystemVerilog in Chapter 3.
Added Latch With Positive Gate and Asynchronous Reset Coding Example (Verilog)
in Chapter 3.
Added a Caution to VHDL Assert Statements in Chapter 4.
Modified Setting up Vivado to use VHDL-2008 in Chapter 5.
Modified VHDL-2008 Language Support in Chapter 5.
Described the unconstrained behavior for VHDL 2008 in Types in Chapter 5.
Modified Multiplexer Case Statement Example (Verilog) in Chapter 6.
Marked $clog2 as supported only in SystemVerilog in Table 6-5.
Added “all others” to Table 6-5.
