1
Continuous-Time Sigma-Delta ADCs
Scott D. Kulchycki, National Semiconductor
C
ontinuous-time sigma-delta (CT
∑
Δ) analog-to-digital
(A/D) conversion technology shatters the conventional
wisdom that pipeline analog-to-digital converters
(ADCs) are the only conversion technique available for high
dynamic performance, sub-100 MSPS (mega-samples per
second) applications. Besides providing more power-effi cient
operation, CT
∑
Δ technology also offers unique features that
greatly reduce the challenges of deploying such ADCs in
high-speed, high-performance systems. In short, CT
∑
Δ
technology means:
• An inherently power-effi cient architecture that eliminates
the high-speed gain stages required for sampled-input
ADCs, such as pipeline or traditional discrete-time (DT)
∑
Δ
(DT
∑
Δ) ADCs.
• An essentially alias-free Nyquist band that is made avail-
able by exploiting inherent over-sampling, an internal
lowpass CT loop fi lter, and on-chip digital fi ltering.
• A purely resistive input with no switching, which is easier
to drive and couples less noise to the overall system than
the switching input capacitors of a sampled-input ADC,
such as a pipeline or DT
∑
Δ ADC.
• An on-chip clock conditioning circuit to provide the
over-sampling clock to the internal modulator. This circuit
increases the frequency and the quality of the input clock,
yielding a low-jitter sampling edge and achieving
high-resolution performance without an expensive,
high-performance input clock.
• Easier migration to future CMOS process technologies.
In a CT
∑
Δ ADC, the impact of noise and nonlinearity
associated with the sampling process is signifi cantly
reduced, allowing for the reduced supply voltages
required for future CMOS processes.
Taken together, the inherent benefi ts of CT
∑
Δ technology and
the opportunity to implement an on-chip clock conditioner
greatly simplify the signal path design by:
• Reducing power requirements.
• Eliminating the need (or reducing the requirements) for an
external anti-aliasing fi lter.
• Reducing the input driver requirements.
• Mitigating the need for high-quality clock sources without
sacrifi cing performance.
Furthermore, the ability of CT
∑
Δ ADCs to scale with technol-
ogy will allow such designs to take full advantage of future
CMOS processes.
National’s CT
∑
Δ technology supports high-resolution ADCs up
to 16 bits and beyond with data output rates up to 100 MHz.
This paper will fi rst review the ADC landscape and explain
how CT
∑
Δ technology is positioned within that space.
Next, the details and benefi ts of CT
∑
Δ technology as applied
to ADCs will be presented, focusing on the advantages and
benefi ts of National’s new ADC12EU050 versus competing
ADC technologies for high-resolution, sub-100 MSPS appli-
cations. Finally, the paper concludes with a summary of the
potential of CT
∑
Δ ADCs.
Data Conversion Fundamentals
ADCs perform two basic, fundamental operations: discretization
in time and discretization in amplitude. The two functions are
shown conceptually in Figure 1, though the actual ADC may not
be structured as such.
The fi rst operation of the ADC is to discretize in time, or
sample, the continually time-varying input analog signal. The
input signal is typically sampled at uniformly spaced times at
a frequency of f
S
, and the samples are thus separated by a
period T
S
= 1/f
S
. Once the input signal is sampled, the resultant
exists only as impulses at the sampling interval, kT
S
. However,
this sampled signal is still able to assume an infi nite range of
values, and therefore cannot be represented precisely in a
digital form.
January 2008
x(t)
x
s
(kT)
f
s
x
D
[k]
n
x
D
[k]
x
s
(t)
x(t)
+Vref
2
+Vref
2
-Vref
2
-Vref
2
k
T
2T 3T
4T 5T 6T
T
2T 3T
4T 5T 6T
10
11 11
1 2 3
4 5 6
01 01
00
Figure 1: Analog-to-digital conversion
