Rev. 0.0, Jan.2009
S5PV210
RISC Microprocessor
Revision 1.10
May 2010
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© 2010 Samsung Electronics Co., Ltd. All rights reserved.
Samsung Confidential
配置寄存器时查看
Rev. 0.0, Jan.2009
Important Notice
The information in this publication has been carefully
checked and is believed to be entirely accurate at the
time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from the
use of the information contained herein.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of any
product or circuit and specifically disclaims any and all
liability, including without limitation any consequential
or incidental damages.
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
Samsung products are not designed, intended, or
authorized for use as components in systems intended
for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
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for any such unintended or unauthorized application,
the Buyer shall indemnify and hold Samsung and its
officers, employees, subsidiaries, affiliates, and
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personal injury or death that may be associated with
such unintended or unauthorized use, even if such
claim alleges that Samsung was negligent regarding
the design or manufacture of said product.
S5PV210 RISC Microprocessor
User's Manual, Revision 1.10
Copyright © 2010 Samsung Electronics Co., Ltd.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu
Yongin-City, Gyeonggi-Do, Korea 446-711
TEL : (82)-(31)-209-0810
FAX : (82)-(31)-209-0837
Home Page: http://www.samsungsemi.com
Printed in the Republic of Korea
Samsung Confidential
Rev. 0.0, Jan.2009
Revision History
Revision No. Date Description Author(s)
1.00 03 04, 2010 - Initial draft G.H.CHA
1.10 05 03 2010 - first updated G.H.CHA
Revision Descriptions for Revision 1.10
Chapter (Rev 1.10)
Chapter Name Page
Subjects (Major changes comparing with last version)
1-2
Block Diagram and Key feature are updated.
1-3
"JPEG codec supports up to 80 Mpixels/s" is removed. The content is
indefinite.
1. Overview
1-7
Maximum size of JPEG Compression/decompression is changed from
65536x65536 to 8192x8192
1-2
Add description about "Device ID" bit field
3-2
3.2.1 Added a description for recommending using 24MHz crystal as
XXTI/XUSBXTI input.
3-2
3.2.1 Modified HDMI part of Figure 3-2
3-3
3.2.2 Added a description for HDMI PHY
3-4
3.3 Modified descriptions some points
3-5
3.3.1 Modified the recommended PMS values for 800MHz, 1GHz from
(6,200,1) (6, 250,1) to (3,100,1) (3,125,1)
3-9
3.4 Modified Figure 3-3 to add the USB HOST PHY input and output
clock.
3-10
3.4 Added the "caution" for using glitch free mux.
3-12
3.5 Removed the description for PLL turn off and added a description as
"Once you turned on any PLL, do not turn off that".
3-13
3.6.1 Added the frequency range of special clocks and modified Table 3-
7.
3-19
3.7.2.1 Added lock time setting guide for PLLs.
3-25
3.7.2.4 Modified usable range of Fref . 1MHz ≤ Fref ≤ 10MHz
3-35
3.7.4 Modified max. operating freq. of SCLKAPLL from 800MHz to 1GHz.
3-40
3.7.5.2 CLK_JPEG[28] in CLK_GATE_IP0 is modified to reserved region
(CLK_JPEG -> Reserved)
3-52/53
3.7.6.1 Modified register descriptions and Figure 3-4 for better
understanding.
ALL
* Globally deleted descriptions for SPI2 and HOST IF
2. System
4-5/6
4.3.1 Modified Table 4-3 for better understanding and missing points of
sub-blocks, audio block, top block and wakeup time. Also, wakeup time is
III
Chapter (Rev 1.10)
Chapter Name Page
Subjects (Major changes comparing with last version)
calculated based on 24Mhz input clock.
4-7
4.3.2 Removed max. 100us lock time, miss printing.
4-16
4.4 Removed a Figure - Internal Operation During Power Mode Transition
that might lead to confusion.
4-17
4.4.1 Modified wakerup source of DeepIdle mode with TOP block on as
all interrupt source.
4-24
4.7 Modified ADC power in sleep mode as "power-on".
4-26
4.7.4 Modified some description of PLL for better understanding.
4-27
4.7.4.1 Modified the clock status after wakeup for each low power mode
of Table 4-8.
4-32/33
4.9.2 Modified power on/off and sleep mode enter/exit sequence for
better understanding.
4-36
4.9.2 Modified initializing condition of inform registers by several resets.
Inform 4~6 are reset by only alive POR. Inform 0~3 are reset by WDT
reset, XnReset and alive POR.
4-41
4.10.4.1 Modified CFG_STANDBYWFI description of PWR_CFG ( 00 :
IDLE mode, 01 : DEEPIDLE mode, 10 : STOP/DEEPSTOP mode )
4-41
4.10.4 Removed PWR_MODE register because the need.
4-47/48
4.10.4.9/10/11/12/13 Added descriptions to calculate time and example
for OSC_FREQ, OSC_STABLE, PWR_STABLE, CLAMP_STABLE,
MTC_STABLE.
4-53
4.10.5.4 Added descriptions for USB PHY0(=OTG device), USB
PHY1(=HOST).
3. Address Space 3-2
Read-only area (0x003FFD00 ~ 0x003FFDFF) is renamed to Security
Area.
The bit properties for all OPRSEL register bits are corrected from ‘R/W’ to
‘W’.
Bit description for OPRSEL register is modified for better understandings.
4-3
Note 4 is added:
User must set both OPRSEL[1] and OPRSEL[3] at the same time.
4. Boot Loader
4-4
Bit description for OPRMON register is modified for better
understandings.