Samsung-S5PV210 cortex-a8手册

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Samsung-S5PV210 cortex-a8 应用开发手册。
List of Figures Figure Title Page Number Number Figure 1-1 S5PV210 Block Diagram 1-2 Figure 2-1 Address Map 2-1 Figure 2-2 Internal Memory Address Map 2-3 Figure 3-1 S5PV210 Pin assignment (584-FCFBGA)Bottom View Figure 3-2 S5PV210 Package Dimension (584-FCFBGA)-Top view ,3-51 Figure 3-3 S5PV210 Package Dimension(584-FCFBGA)-Side view 3-52 List of tables Table Title Page Number Number Tabe31S5PV210584 FCFBGA Pin Assignment- Pin number order(1/4)……… Table 3-2 S5PV210 584 FCFBGA Pin Assignment- Pin Number Order(2/4) Table 3-3 S5PV210 584 FCFBGA Pin Assignment- Pin Number Order (3/4)............... Tabe3-4s5PV210584 FCFBGA Pin Assignment- Pin number order(4/4)……… Table 3-5 S5PV210 Power Pin to Ball Assignment (12) 246802 Table 3-6 S5PV210 Power Pin to Ball Assignment (2/2 S5PV210 UM 10BOVERVIEW OF S5PV210 OVERVIEW OF S5PV210 1.1 ARCHITECTURAL OVERVIEW S5PV210 is a 32-bit RISC cost-effective, low power, and high performance microprocessor solution for mobile phones and general applications. It integrates the ARM Cortex-A8 core, which implements the ARM architecture V7-A with supporting peripherals To provide optimized hardware(H/) performance for the 3G and 3. 5G communication services, S5PV210 adopts 64-bit internal bus architecture. This includes many powerful hardware accelerators for tasks such as motion video processing, display control, and scaling. Integrated Multi Format Codec(MFC)supports encoding and decoding of MPEG-1/214, H 263, and H. 264, and decoding of vC1 and Divx. This hardware accelerator (MFC) supports real-time video conferencing and Analog Tv out, HDMI for NTSC, and PAL mode S5PV210 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access and DRAM port to meet high bandwidths DRAM controller supports LPDDR1(mobile DDR), DDR2, or LPDDR2 Flash/ROM port supports NAND Flash, NOR-Flash, OneNAND, SRAM, and rom type external memory To reduce the total system cost and enhance the overall functionality, S5PV210 includes many hardware peripherals such as TFT 24-bit true color LCD controller, Camera Intertace, MIPI DSl, CSl-2, System Manager for power management, ATA interface, four UARTS, 24-channel DMA, four Timers, General I/O Ports, three 12S, S/PDIF, three IIC-BUS interface, two HS-SPL, USB Host 2.0, USB 2.0OTG operating at high speed(480Mbps). four SD Host and high-speed Multimedia Card Interface, and four PLLs for clock generation Package on Package(POP)option with MCP is available for small form factor applications AMSUN ELECTRONICS S5PV210 UM 10BOVERVIEW OF S5PV210 1.2 BLOCK DIAGRAM OF S5PV210 Figure 1-1 shows the complete block diagram of S5PV210 System Peripheral CPU Core Multimedia RTC CortexEs PLLX4 12 MP Camera IF/MIPI CS-2 32KB/32KB ID cache Timer with PWM4ch 800MHz/1GHz@1.1V/12V 1080p 30 fps MFC Watchdog timer Codec h 263/H. 264/MPEG4 Decoder MPEG2/VC-1/Divx DMA(24ch) 512KB NEO L2 cache Keypad (14X8 2DVG/ 3 D Graphics engine TS- ADC(12bit/10 NTSC/ PAL TV out Connectivity HDMI Audio F 64 KB RAM Ssx3/PCM×3 ROM EG codec SPDIF/AC97 Multi layer AHB/AXI Bus TFT LCD controller XGA resolution Storage IF HSMMC SD X4 Engines DSP ATA Memory Interface SRAM/ ROM Connectivity USB Host 2./OTG20 1 UART X4 Power Flex)OneNAND Management lIC x3 SLC/ MLC NAND HS-SP1x2 with 16 bit ecc Clock gating/ Power gating/ Modem IF(16KB DPSRAM) Dynamic Voltage LPDDR1/One DRAM Fre g LPDDR2/DDR2 GPIO Figure 1-1 S5PV210 Block Diagram AMSUN ELECTRONICS 12 S5PV210 UM 10BOVERVIEW OF S5PV210 1.3 KEY FEATURES OF S5PV210 The key features of S5PV210 include ARM CortexTM-A8 based CPU Subsystem with NEON 32/32 KB I/D Cache 512 KB L2 Cache Operating frequency up to 800 MHz at 1.1V, 1 GHz at 1.2V 64-bit Multi-layer bus architecture MSYS domain for ARM CortexTM-A8, 3D engine, Multi Format Codec and Interrupt Controller Operating frequency up to 200 MHz at 1.1V DSYS domain mainly for Display IPs (such as LCD controller, Camera interface, and TOut), and MDMA Operating frequency up to 166 MHz at 1.1V PSYs domain mainly for other system component such as system peripherals, external memory interface peri DMAs, connectivity IPs, and Audio interfaces Operating frequency up to 133 MHz at 1.1V Audio domain for low power audio play Advanced power management for mobile applications 64 KB ROM for secure booting and 128 KB RAM for security function 8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution Multi Format Codec provides encoding and decoding of MPEG-4/H 263/H. 264 up to 1080p@30fps and decoding of MPEG-2/C1/Divx video up to 1080p@30 fps JPEG codec supports up to 80 Mpixels/s 3D Graphics Acceleration with Programmable shader up to 20M triangles/s and 1000 Mpixels/s 2D Graphics Acceleration up to 160Mpixels/s 1/2/4/8 bpp Palletized or 8/16/24 bpp Non-Palletized Color TFT recommend up to XGA resolution TV-out and HDMI interface support for NTSC and PAL mode with image enhancer MIPI-DSI and MlPl-CSI intertace support One Ac-97 audio codec interface and 3-channel PCM serial audio interface Three 24-bit 12S interface support One TX only S/PDIF interface support for digital audio Three 12C interface support TWo SPI support Four UART supports three Mbps ports for Bluetooth 2.0 On-chip USB 2.0 OTG supports high-speed(480 Mbps, on-chip transceiver) On-chip USB 2.0 Host support Asynchronous Modem Interface support Four SD/ SDIO/ HS- MMC interface support ATA/ ATAPl-6 standard interface support AMSUN ELECTRONICS S5PV210 UM 10BOVERVIEW OF S5PV210 24-channel DMA controller( 8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA) Supports 14x8 key matrix 10-channel 12-bit multiplexed ADC · Configurable GPos Real time clock, PLL, timer with PWM and watch dog timer System timer support for accurate tick time in power down mode(except sleep mode Memory Subsystem Asynchronous SRAM/ ROM/ NOR Interface with x8 or x16 data bus NAnd Interface with x8 data bus Muxed/ demuxed onenand Interface with x16 data bus LPDDR1 Interface with x16 or x32 data bus(266-400 Mbps/ pin DDR) DDR2 interface with x16 or x32 data bus(400 Mbps/ pin DDR) LPDDR2 interface(400 Mbps/ pin DDR) 1.3.1 MICROPROCESSOR The key features of this microprocessor include The ARM CortexTM-A8 processor is the first application processor based on ARMv7 architecture With the ability to scale in speed from 600 MHz to 1 GHz (or more), the ARM CortexTM-A8 processor meets the requirements of power-optimized mobile devices, which require operation in less than 300mW; and performance-optimized consumer applications require 2000 Dhrystone MIPS Supports first superscalar processor featuring technology from aRm for enhanced code density and performance, NEONTM technology for multimedia and signal processing and jazellee rct technology for ahead-of-time and just-in-time compilation of Java and other byte code languages Other features of arm cortexTM-A8 include Thumb-2 technology for greater performance, energy efficiency, and code density NeoNTM signal processing extensions Jazelle rct Java-acceleration technology Trustzone technology for secure transactions and DRM 13-stage main integer pipeline 10-stage NEONTM media pipeline Integrated L2 Cache using standard compiled RAMs Optimized l 1 caches for performance and power AMSUN ELECTRONICS S5PV210 UM 10BOVERVIEW OF S5PV210 1.3.2 MEMORY SUBSYSTEM The key features of memory subsystem include High bandwidth Memory Matrix subsystem Two independent external memory ports (1 x16 Static Hybrid Memory port and 2 X32 DRAM port) Matrix architecture increases the overall bandwidth with simultaneous access capability SRAM ROM NOR Interface o x8 or x16 data bus o Address range support: 23-bit o Supports asynchronous interface Supports byte and half-word access Onenand Interface o x16 data bus o Address range support: 16-bit o Supports byte and half-word access o Supports 2 KB page mode for OneNAND and 4 KB page mode for Flex OneNAND o Supports dedicated DMA NAND Interface o Supports industry standard nand interface o x8 data bus LPDDR1 Interface o 32 data bus with 400 Mbps/ pin Double Data Rate(DDR) o 1.8V interface voltage o Density support up to 4-Gb per port (2CS) DDR2 Interface o 32 data bus with 400 Mbps/ pin double data rate(DDR) o 1.8V intertace voltage o Density support up to 1-Gb per port (2CS, when 4bank DDR2 o Density support up to 4-Gb per port (1CS, when 8bank DDR2 LPDDR2 interface o 32 data bus with up to 400 Mbps/pin o 1.2V interface voltage o Density support up to 4-Gb per port(2CS) AMSUN ELECTRONICS S5PV210 UM 10BOVERVIEW OF S5PV210 1.3.3 MULTIMEDIA The key features of multimedia include Camera Interface Multiple input support o ITU-R BT 601/656 mode o DMA (AX 64-bit interface)mode MIPI(CSI)mode Multiple output support o DMA(AXI 64-bit interface)mode o Direct fIFO mode Digital Zoom In(DZI)capability Multiple camera input support Programmable polarity of video sync signals Input horizontal size support up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution Image mirror and rotation(X-axis mirror, Y-axis mirror, 90, 180, and 270 rotation) Various image formats generation Capture frame control support Image effect support Multi-Format video CodeC(MFC) TU-TH.264,lsO/EC14496-10 o Decoding supports Baseline/ Main/High Profile Level 4.0(except Flexible Macro-block Ordering (FMO), Arbitrary Slice Ordering(Aso)and Redundant Slice(Rs)) o Encoding supports Baseline/ Main/ High Profile(except FMO, Aso, and rs) ITU-TH 263 Profile level 3 o Decoding supports Profile3, restricted up to SD resolution 30 fps(H 263 Annexes to be supported Annex I: Advanced Intra Coding Annex J: De-blocking(in-loop filter Annex k: slice structured mode without fmo aso Annex T: Modified Quantization Annex D: Unrestricted motion vector mode Annex F: Advanced Prediction Mode except overlapped motion compensation for luminance Encoding supports Baseline Profile( supports customer size up to 1920x 1088) ISO/EC 14496-2 MPEG-4 and divx o Decoding supports MPEG-4 Simple/ Advanced Simple Profile Level5 o Decoding supports DivX Home Theater Profile(version 3. XX, 4.XX, 5.XX, and 6.1), Xvid Encoding supports MPEG-4 Simple/ Advanced Simple Profile AMSUN ELECTRONICS 16

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wenbbo 像字典一样,对开发人员有一定的参考价值。下载扣分太多!
2014-04-09
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houhuaide 这份资料太有价值了.多谢!
2013-11-14
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wosicola 虽然贵点,不过解决了需要,也行了
2013-04-18
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leaez 现在三星网站也可以下载了
2013-04-17
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Dengwj2010 一个IC资料需5个积分太贵,不过有需要!谢谢
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您会向同学/朋友/同事推荐我们的CSDN下载吗?
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