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FEBRUARY 2020

VOLUME 55

NUMBER 2

IJSCBC

(ISSN 0018-9200)

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378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020

A 0.3 lx–1.4 Mlx Monolithic Silicon Nanowire

Light-to-Digital Converter With

Temperature-Independent Offset Cancellation

Cyuyeol Rhee , Junyoung Park, Student Member, IEEE, and Suhwan Kim , Senior Member, IEEE

Abstract—This article presents a monolithic light-to-digital

converter (LDC) based on silicon nanowires. The silicon

nanowires are arranged in a conﬁguration, which allows can-

cellation for the offset due to dark leakage current and facil-

itates system-level chopping of the signal chain, including the

nanowires. The readout integrated circuit (ROIC) has an ana-

log front end (AFE) with a resistive-feedback transimpedance

ampliﬁer (TIA) to provide a constant voltage that strongly

biases the nanowires. A programmable-gain switched-capacitor

incremental delta–sigma analog-to-digital converter doubles the

output of the TIA and feeds a digital back end that provides

a decimated output. Finally, system-level chopping reduces the

residual offset and 1/f noise, and 50-/60-Hz rejection suppresses

interference from mains lighting. Fabricated in a 0.18-µmCMOS

process, the LDC has an input-referred current noise density

of 235 fA/

√

Hz, and a dynamic range of 106.7, from 0.3 lx to

1.4 Mlx. The offset from the nanowires and the AFE is reduced

to less than 30 µV and offset drift of 193 nV/°C in a temperature

range of −40 °C–85 °C. The AFE of the LDC draws 59.5 µAat

3.3 V, and the digital back end draws 8 µAat1.8V.

Index Terms— 1/f noise, 50-/60-Hz rejection, dark leakage

current, light-to-digital converter (LDC), programmable-gain

incremental delta–sigma analog-to-digital converter (ADC),

silicon nanowires, system-level chopping.

I. INTRODUCTION

IGHT sensor systems are used in a variety of applications,

such as light energy monitoring, proximity detection,

and non-invasive physiological monitoring [1]–[5]. A light

sensor system, which usually consists of a photodetector and

a readout integrated circuit (ROIC), must be able to handle

a wide range of illumination conditions from a very dark

environment (<1 lx) to bright sunlight (∼1 Mlx) [1], [2].

A light sensor system is usually based on a photodiode

(PD) [1]–[5]. This type of photodetector is widely used

because it has high linearity and is relatively insensitive to

changes in bias voltages. However, PDs require an illumination

area of several square millimeters due to their relatively

low photoresponsivity, making them less suitable for use in

Manuscript received March 15, 2019; revised July 5, 2019 and

September 16, 2019; accepted October 12, 2019. Date of publication

November 7, 2019; date of current version January 28, 2020. This article

was approved by Associate Editor David Stoppa. (Corresponding author:

Suhwan Kim.)

The authors are with the Department of Electrical and Computer Engi-

neering, Seoul National University, Seoul 08826, South Korea, and also

with the Inter-University Semiconductor Research Center (ISRC), College of

Engineering, Seoul 151-742, South Korea (e-mail: suhwan@snu.ac.kr).

Color versions of one or more of the ﬁgures in this article are available

online at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/JSSC.2019.2949257

ROICs [6]. Other types of photodetector can be integrated

into a system on a chip. For example, an array of single-

photon avalanche diodes (SPADs) with a very small area

(∼0.00072 mm

) and high photosensitivity has been integrated

into an ROIC [7]–[9]. However, SPADs require a high voltage

between 8 and 20 V, which involves an extra charge pump,

which increases power consumption [8]–[10], and the sys-

tem with SPADs provides a limited optical dynamic range

of 48 dB [8]. Silicon nanowires do not require high-voltage

biasing, high sensitivity to light and the high surface-to-

volume ratio [6], [11], [12], and, therefore, emerged as a very

promising photodetector.

Light falling on a silicon nanowire creates electron–hole

pairs, and thus, its resistance decreases [6]. This response

is monotonic, but the resulting photocurrent depends on the

voltage applied to the nanowire [6], [11]. A nanowire, which

is not illuminated at all, still has a ﬁnite resistance, and if

the voltage is applied, the current will ﬂow. This is called the

dark leakage current. The equivalent resistance of a silicon

nanowire at a speciﬁc bias voltage varies with temperature,

even in very low illumination [14], [17], which means that

the offset arising from the dark leakage current is sensitive

to temperature. When silicon nanowires are integrated with

other circuits, this current can be affected by waste heat

from other circuits, as well as the ambient temperature. The

offsets produced not only by the dark leakage current but also

by the ROIC are generally undesirable and are cumbersome

when temperature changes because a one-time calibration is

not enough to eliminate offset errors across all temperature.

Therefore, these offsets must be suppressed over the operating

temperature range.

To overcome these issues, we present a monolithic light-

to-digital converter (LDC), which compensates for the offset

voltages generated by dark leakage current and ROIC, over

its entire temperature range. This LDC consists of a silicon

nanowire sensor (R

), a dark cell (R

), an analog front end

(AFE), a digital back end, and peripheral blocks. The AFE,

which largely determines the performance of the LDC, con-

sists of a resistive-feedback transimpedance ampliﬁer (TIA)

and a programmable-gain switched-capacitor (SC) incremental

delta–sigma () analog-to-digital modulator. Within the

TIA, a chopping technique is combined with a ripple-reduction

loop (RRL) to achieve constant biasing of the sensor, low

1/ f noise corner, and a reduced offset. This TIA operates

in conjunction with system-level chopping, which takes place

See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

RHEE et al.: 0.3 lx–1.4 Mlx MONOLITHIC SILICON NANOWIRE LDC WITH TEMPERATURE-INDEPENDENT OFFSET CANCELLATION 379

across the entire system, including the sensor, to eliminate

the offset due to dark leakage current and the ROIC, across

the operating temperature range. System-level chopping also

reduces the residual 1/ f noise and sensor bias voltage. This

eliminates the need for offset calibration when the sensor is

interfaced with the ROIC. A digital rejection ﬁlter notches out

50-/60-Hz noise from any mains light source.

The remainder of this article is organized as follows.

In Section II, we describe silicon nanowires. In Section III,

we introduce the LDC. Section IV is devoted to the details of

the TIA. In Section V, we introduce the programmable-gain

SC incremental  analog-to-digital converter (ADC). Exper-

imental results are presented in Section VI. We draw conclu-

sions in Section VII.

II. S

ILICON NANOWIRESASALIGHT-SENSING ELEMENT

Silicon nanowires can be constructed by bottom–up or

top–down fabrication. Bottom–up fabrication is synthesis-

based, which is incompatible with the standard process of

CMOS ICs [15], [16]. In this case, nanowires and ICs must

be connected by wire bonding, resulting in a high packaging

cost. A sensing system created in this manner would be

large and noisy due to the parasitic capacitance formed by

the bonding process. An integrated conﬁguration of silicon

nanowires can be produced by top–down fabrication, such as

photolithography and etching [6], [13]–[16].

Within a CMOS standard process, silicon nanowires, such

as that shown in Fig. 1(a) and (b), can be produced by

the following fabrication process. A p-type substrate lightly

doped with boron is prepared, and thermal oxide is grown

by a wet oxidation process. Line patterns of 0.5 μmare

deﬁned by a photolithography process, and rectangular sil-

icon columns are fabricated by silicon reactive ion etching

process. Afterward, a wet etching process using tetramethy-

lammonium hydroxide (TMAH) solution forms hour-glass-

shaped structures. In this process, anisotropic wet etching is

performed utilizing that the etch rate of (111)-plane is more

than one hundred times slower than that of the (100)-plane.

Then, the second wet oxidation process is performed to fabri-

cate triangular-shaped silicon nanowires by thermal oxidation.

Gaps between the silicon nanowires are ﬁlled with oxida-

tion layer by high-density plasma chemical vapor deposition

(HDPCVD). Silicon nanowires are covered with oxide and

nitride passivation layer. After fabrication of silicon nanowires,

CMOS circuits are processed. The CMOS process provides

four interconnect layers (metal 1 –metal 4). The dark cell is

shielded by placing the metals available in the CMOS process

on the top of the dark cell [18]–[22]. Fig. 1(c) is a scanning

transmission electron microscope (STEM) image of a silicon

nanowire with a width of 300 nm. Fig. 2 is the equivalent

electrical model of the sensor, which is an array of silicon

nanowires. The model consists of an equivalent resistance R

a shunt capacitance C

, and two parasitic capacitances C

and C

due to interconnections to the terminals of the silicon

nanowires. Rs decreases from a few G down to 11 M as

the light intensity changes from 0 lx to 28 000 lx. C

can be

ignored in a relatively slow system, which is likely to have

Fig. 1. (a) Arrangement of CMOS-compatible silicon nanowires in an array.

Metal connections to contact holes are not shown. (b) Top view of an array of

silicon nanowires and the dark cell (white). (c) STEM image of the vertical

cross section view [dashed line in Fig. 1(a)] of a silicon nanowire.

Fig. 2. Electrical model of the silicon nanowire sensor.

Fig. 3. Monolithic silicon nanowire LDC.

a bandwidth below 10 Hz. On-chip integration of the sensor

and the ROIC can keep the values of C

and C

smaller

than a few hundred femtofarads.

III. M

ONOLITHIC LDC

The LDC shown in Fig. 3 consists of a silicon nanowire

sensor, a dark cell, a TIA, an incremental  modulator,

a digital back end, and peripherals, such as a bandgap voltage

reference (BGR), a low-dropout (LDO) voltage regulator, and

an oscillator. The sensor R

is an array of silicon nanowires,

380 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020

Fig. 4. Architecture of the analog front end and its timing diagram.

and the dark cell R

is a duplicate of the sensor, except that it

is covered and surrounded by metal layers. There is chopping

on the entire system from sensor bias voltages to the output

of the modulator by F

SYS

, and a decimation ﬁlter decimates

the modulator’s output bs and provides a robust rejection

capability. The decimated 18-bit digital codes D

OUT

are passed

through a serial communication in the digital back end. The

internal oscillator generates a 4-MHz clock signal for I

C and

SPI for serial communications. The clock generator receives an

86.4-kHz clock signal from the digital back end and generates

a 21.6-kHz clock signal F

for chopping the main ampliﬁer

in the TIA and the RRL and 90° shifted sampling clock

signal F

for the  modulator. A voltage V

of 3.3 V

biases the sensor and provides the reference voltage to the

 modulator. The BGR and LDO generate 1.8-V supply

for the digital circuits. A biasing circuit distributes a current

of 200 nA to bias ampliﬁers in the TIA and the  modulator.

The system can save energy by going into sleep mode after a

conversion. The power-on reset (POR) puts the system into a

known state after wakeup.

The architecture of the AFE and its timing diagram are

shown in Fig. 4. The transimpedance gain of the TIA can

be controlled from 200 k to 10 M to accommodate the

wide dynamic range of ambient light while providing sub-lx

resolution. To achieve sub-lx resolution, the AFE requires the

transimpedance gain of 10 M and a 16.5-bit ADC, with

a single-ended operation of the TIA. This corresponds to a

noise voltage of 20 μV

rms

in the band of interest. The 

modulator has a gain of 2, but its integrators are not saturated

at full-scale input because the output of the TIA and the

common-mode voltage V

are connected to the differential

inputs of the modulator. The noise and offset of the readout IC

are primarily suppressed by a chopping scheme in the TIA.

The chopping ripple of the input stage is suppressed by a

continuous-time RRL to provide constant biasing of the sensor.

Asinc

ﬁlter is used for decimation, and a ﬁnite impulse

response ﬁlter provides a moving average of the SINC

OUT

signal for system-level chopping.

IV. I

MPLEMENTATION OF THE TIA

A. Sensor Conﬁguration

In LDCs based on PDs, a dark PD is used to cancel a sensing

PD’s dark leakage current by connecting the sensing PD to one

input of a differential TIA and a dark PD to the other input,

as shown in Fig. 5(a) [18]–[22]. Since the equivalent resistance

of a PD is large and insensitive to light intensity, the circuit

in Fig. 5(a) does not affect the input common-mode voltage

of the TIA. However, if silicon nanowires are substituted

for the PDs, as shown in Fig. 5(b), the voltage across the

sensor will vary, changing the relationship between light

intensity and current. Fig. 5(c) shows the dc common-mode

equivalent circuit if the circuit described in Fig. 5(b). The input

common-mode voltage V

IN,dc

of the ampliﬁer would vary as

follows:

IN,DC

= V

TIACOM

+ R

(1)

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