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Hindawi Publishing Corporation

VLSI Design

Volume 2010, Article ID 213043, 11 pages

doi:10.1155/2010/213043

Research Article

FPGA Implementation of an Amplitude-Modulated

Continuous-Wave Ultrasonic Ranger Using Restructured

Phase-Locking Scheme

P. Sumathi

and P. A. Janakiraman

DA-IICT, Department of Information and Communication Technology, Gandhinagar, Gujarat 382007, India

Indian Institute of Technology Madras, Department of Electrical Engineering, Chennai 600036, India

Correspondence should be addressed to P. Sumathi, sumichan04@yahoo.co.in

Received 30 May 2009; Revised 9 September 2009; Accepted 8 December 2009

Academic Editor: Ethan Farquhar

Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is

properly cited.

An accurate ultrasonic range ﬁnder employing Sliding Discrete Fourier Transform (SDFT) based restructured phase-locked loop

(RPLL), which is an improved version of the recently proposed integrated phase-locking scheme (IPLL), has been expounded.

This range ﬁnder principally utilizes amplitude-modulated ultrasonic waves assisted by an infrared (IR) pilot signal. The phase

shift between the envelope of the reference IR pilot signal and that of the received ultrasonic signal is proportional to the range.

The extracted envelopes are ﬁltered by SDFT without introducing any additional phase shift. A new RPLL is described in which

the phase error is driven to zero using the quadrature signal derived from the SDFT. Further, the quadrature signal is reinforced

by another cosine signal derived from a lookup table (LUT). The pulse frequency of the numerically controlled oscillator (NCO)

is extremely accurate, enabling ﬁne tuning of the SDFT and RPLL also improves the lock time for the 50 Hz input signal to 0.04 s.

The percentage phase error for the range 0.6 m to 6 m is about 0.2%. The VHDL codes generated for the various signal processing

steps were downloaded into a Cyclone FPGA chip around which the ultrasonic ranger had been built.

1. Introduction

Ultrasonic sensors ﬁnd applications generally in distance

measurement, indoor mobile robot control, for environment

information, gleaning, localization, and map building, vibra-

tion measurements, and safety systems like intelligent airbag

control [1–4]. Many range-ﬁnding techniques are found in

the literature, based on either the time of ﬂight (TOF) or

the continuous wave method [5–7]. A variety of continuous

wave methods have been reported; notable among them

are based on the multifrequency and amplitude-modulated

(AM) schemes [8, 9]. The signiﬁcant advantages of the AM

continuous-wave method over the TOF were presented in

[10]. The phase shift observed in the ultrasonic wave with

respect to the distance traveled can be used to measure the

range. For a 40 kHz sound wave, the maximum measurable

range using phase shift is only 8.6 mm. In the present

work, to enhance the measurable range to 6.86 m, the

ultrasonic signal is amplitude modulated by a 50 Hz signal,

which is more appropriate for mobile robot localization and

navigation in indoor applications.

In this scheme, a low-frequency-modulated Infrared (IR)

is used as a pilot signal. Another ultrasonic signal (US)

modulated by the same low-frequency signal is utilized for

estimating the range. A novel procedure using Sliding Dis-

crete Fourier transform (SDFT) can be employed to extract

the fundamental component of the envelope of the received

ultrasonic signal [11]. The sampling pulse frequency of the

SDFT block is tuned precisely by an integrated phase-locked

loop so that exactly one full period of the envelope signal

can be accommodated in a window of width 128 [12]. Two

such PLL’s, one for the extraction of the sinusoidal envelope

of the infrared pilot signal, and another for ultrasonic signal

are employed in the range-ﬁnding equipment. The PLL is

basically a feedback circuit minimizing the phase error by

correlating the given envelope signal with the quadrature

2 VLSI Design

signal derived from the SDFT block. The envelope of the IR

signal is the reference, against which the phase shift of the

extracted envelope of the amplitude-modulated ultrasonic

signal is compared. The integrated phase-locking scheme

discussed in [12] shows a steady residual error in the NCO

output frequency. The primary focus of the present paper

is to describe the restructured phase-locking scheme, which

makes use of a look up table to assist the quadrature signal

derived from the SDFT block mainly to reduce the residual

phase error. The hardware realization of the restructured

phase-locking scheme which is implemented in an FPGA

chip has also been described. The DSP builder tool, has been

applied extensively for simulation and practical realization of

an ultrasonic range ﬁnder.

The restructured phase locking scheme and its com-

ponents have been described in Section 2.Theproposed

ultrasonic range measurement scheme based on RPLL,

built using the DSP builder tool has been explicated in

Section 3. The simulation and experimental results obtained

using Cyclone FPGA have been presented in Section 4 and

Section 5, respectively. The major conclusions are drawn in

Section 6.

The schematic of the proposed ultrasonic range ﬁnder

is shown in Figure 1(a). This consists of a transmitter and

a receiver unit. The transmitter unit sends an IR pilot

signal as well as an ultrasonic signal, both simultaneously

modulated by a low-frequency sine wave. The receiver unit

contains an IR receiver and an ultrasonic receiver. On the

transmitter side a 40 kHz signal had been used to generate

the ultrasonic carrier and a 50 Hz sinusoidal signal for

amplitude-modulation. The 50 Hz sine wave is converted

into square wave using a limiter circuit for modulating the

IR pilot signal to serve as the instantaneous reference signal.

An ultrasonic transducer transmits the amplitude modulated

40 kHz signal. Figure 1(b) shows the transmitted reference IR

signal, ultrasonic signal, and the received ultrasonic signal.

On the receiver side, the ultrasonic signal is ampliﬁed,

rectiﬁed, and processed by an SDFT-based restructured

phase-locking scheme to extract the sinusoidal envelope.

The received reference IR signal is also processed using

another SDFT based RPLL for extracting the fundamental

component of the envelope. The detailed explanation of this

scheme is presented in the next section.

2. Restructured Phase-Locking Scheme

The operation of the restructured phase locked-loop (RPLL)

based on SDFT is brieﬂy explained here. The detailed block

diagram of RPLL scheme is shown in Figure 2.Whena

periodic input signal is passed through a sliding DFT block

tuned to a particular frequency, two distinct output signals

are obtained. The ﬁrst signal is basically the fundamental

component of the incoming periodic signal, which may,

however, be slightly shifted in phase, whenever the frequency

of the incoming signal deviates from the frequency for which

the SDFT block is tuned [12]. The SDFT block yields another

signal, which is in quadrature with the ﬁrst output signal.

The correlation between the input signal and the quadrature

Tr an sm i tte r

unit

Receiver

unit

transmitter

receiver

Ultrasonic

transmitter

Ultrasonic

receiver

(a)

Amplitude

−0.5

0.5

Amplitude

−0.5

0.5

Amplitude

−1

Time (s)

00.01 0.02 0.03 0.04 0.05

Received ultrasonic signal

Transmitted ultrasonic signal

IR reference

Phase shift

Envelope

(b)

Figure 1: (a) Schematic of the proposed Ultrasonic Range Finder

and (b) IR reference signal, transmitted ultrasonic signal, and

received ultrasonic signal.

signal from the SDFT can be made use of, for adjusting the

frequency of the numerically controlled oscillator (NCO)

which provides the sampling pulses to the SDFT block,

resulting in the phase lock of the SDFT output [12]. Under

these conditions, the enabling or the sampling frequency

= fN,where f is the cyclic frequency of the periodic input

signal and N is the number of samples per cycle. Small phase

errors may still persist which can be greatly reduced by the

addition of an LUT-based pure quadrature signal. Essentially,

this scheme diﬀers from the simple integrated phase-locking

scheme presented in [12]; in that, the quadrature signal

output of the SDFT block is supplemented by a cosine

wave from a lookup table accessed by an address counter

which in turn is driven by NCO pulses. The added cosine

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