Integrated Circuit Module.pdf

This manual describes the features and operation of the inter-integrated circuit (I2C) module that is available on the TMS320x2833x, 2823 device . The I2C module provides an interface between one of these 28x devices and devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. This manual assumes the reader has familiarity with the I2C-bus specification. The I2C module described in this reference guide is a Type 0 I2C. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with an I2C module of the same type, to determine the differences between types, and for a list of device-specific differences within a type. ### Integrated Circuit Module (I2C) - Key Knowledge Points #### Introduction to the I2C Module The Integrated Circuit Module, specifically the Inter-Integrated Circuit (I2C) module, is a communication interface designed for the TMS320x2833x and 2823x devices manufactured by Texas Instruments. This module enables bidirectional serial data transfer between these devices and other components that comply with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. The I2C module discussed in this document is of Type 0 I2C. #### Features The I2C module supports several key features: - **Bidirectional Communication:** It allows both sending and receiving data over a single wire for data (SDA) and a single wire for clock (SCL). - **Addressing Schemes:** Supports both 7-bit and 10-bit addressing formats, as well as a free data format for addressing devices on the bus. - **Data Transfer:** Capable of transferring data in various configurations, including repeated start conditions. - **Interrupt Handling:** Generates interrupt requests for various events such as data reception, transmission completion, and error conditions. - **Clock Synchronization:** Ensures proper synchronization of data transfer by generating and managing the clock signal. - **Arbitration:** Handles multiple masters on the bus by providing a mechanism for determining which master takes control of the bus. #### Features Not Supported Some features are not supported by the I2C module: - High-speed mode - Multi-master mode with automatic arbitration loss detection - Clock stretching beyond the maximum frequency #### Functional Overview The I2C module operates based on a set of rules and signals: - **Start and Stop Conditions:** These are used to initiate and terminate data transfers. A start condition is generated by a falling edge on SDA while SCL is high, and a stop condition is generated by a rising edge on SDA while SCL is high. - **Data Validity:** Data on the SDA line must be stable when SCL is high. - **Clock Synchronization:** The module generates the clock signal and ensures it is synchronized with data transfer. - **Arbitration:** In case two or more masters attempt to access the bus simultaneously, the module implements a process to determine which master should proceed. #### Clock Generation The I2C module uses a prescaler register and clock divider registers to generate the clock signal. The prescaler register (I2CPSC) determines the base clock frequency, and the clock divider registers (I2CCLKL and I2CCLKH) further divide the clock to achieve the desired clock rate. #### I2C Module Operational Details The operational details of the I2C module include: - **Input and Output Voltage Levels:** The module operates within specific voltage levels to ensure compatibility with different devices. - **Data Transfer Modes:** Supports standard and fast modes with a maximum data rate of 100 kbps and 400 kbps, respectively. - **Serial Data Formats:** Specifies how data is formatted and transmitted, including the use of 7-bit or 10-bit addresses. - **NACK Bit Generation:** The module can generate a non-acknowledge (NACK) bit if it detects an error or needs to terminate data transfer prematurely. - **Clock Synchronization:** The module manages the clock signal to ensure data integrity during transfer. #### Interrupt Requests Generated by the I2C Module The I2C module generates interrupt requests for various events: - **Basic I2C Interrupt Requests:** Include events such as data reception and transmission completion. - **I2C FIFO Interrupts:** Triggered by the status of the transmit and receive FIFOs. #### Resetting/Disabling the I2C Module To reset or disable the I2C module, specific control bits in the I2C Mode Register (I2CMDR) need to be set or cleared. #### I2C Module Registers The I2C module includes several registers for configuration and status monitoring: - **I2C Mode Register (I2CMDR):** Controls the operating mode, addressing format, and enables/disables various features. - **I2C Extended Mode Register (I2CEMDR):** Provides additional configuration options. - **I2C Interrupt Enable Register (I2CIER):** Enables or disables specific interrupt sources. - **I2C Status Register (I2CSTR):** Contains status information about ongoing operations. - **I2C Interrupt Source Register (I2CISRC):** Indicates the source of the current interrupt request. - **I2C Prescaler Register (I2CPSC):** Sets the base clock frequency. - **I2C Clock Divider Registers (I2CCLKL and I2CCLKH):** Further divides the clock signal. - **I2C Slave Address Register (I2CSAR):** Stores the address of the slave device being communicated with. - **I2C Own Address Register (I2COAR):** Defines the address of the local device. - **I2C Data Count Register (I2CCNT):** Specifies the number of bytes to be transferred. - **I2C Data Receive Register (I2CDRR):** Contains received data. - **I2C Data Transmit Register (I2CDXR):** Holds data to be transmitted. - **I2C Transmit FIFO Register (I2CFFTX):** Stores data to be transmitted. - **I2C Receive FIFO Register (I2CFFRX):** Receives incoming data. These registers provide detailed control and status information necessary for configuring and monitoring the I2C module's operations. Understanding and utilizing the I2C module effectively requires familiarity with the I2C-bus specification and the specific capabilities and limitations of the TMS320x2833x and 2823x devices.