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Synthesis and Simulation Design Guide
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Synthesis and Simulation Design Guide from Xilinx
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Synthesis and Simulation Design Guide Printed in U.S.A.
Synthesis and Simulation
Design Guide
Synthesis and Simulation Design Guide
ii Xilinx Development System
“Xilinx” and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted
herein are reserved.
CoolRunner, RocketChips, RocketIP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090,
XC4005, and XC5210 are registered trademarks of Xilinx, Inc.
The shadow X shown above is a trademark of Xilinx, Inc.
ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable
Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap,
Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA,
LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze,
PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, Rocket I/O, SelectI/O, SelectRAM, SelectRAM+, Silicon
Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap,
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Xilinx XDTV, Xinfo, XSI, XtremeDSP, and ZERO+ are trademarks of Xilinx, Inc.
The Programmable Logic Company is a service mark of Xilinx, Inc.
All other trademarks are the property of their respective owners.
Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown
herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others.
Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and
to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described
herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown
or described herein "as is." By providing the design, code, or information as one possible implementation of a
feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims
of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx
expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including
but not limited to any warranties or representations that the implementation is free from claims of infringement, as
well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and
products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent
that devices shown or products described herein are free from patent infringement or from any other third party
right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of
any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any
engineering or software support or assistance provided to a user.
Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in
such applications without the written consent of the appropriate Xilinx officer is prohibited.
The contents of this manual are owned and copyrighted by Xilinx. © Copyright 1994-2002 Xilinx, Inc. All Rights
Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished,
downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic,
mechanical, photocopying, recording or otherwise, without the prior written consent of Xilinx. Any unauthorized
use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and
publicity, and communications regulations and statues.
R
Synthesis and Simulation Design Guide iii
About This Manual
This manual provides a general overview of designing Field
Programmable Gate Arrays (FPGAs) with Hardware Description
Languages (HDLs). It includes design hints for the novice HDL user,
as well as for the experienced user who is designing FPGAs for the
first time.
The design examples in this manual were created with Verilog and
VHSIC Hardware Description Language (VHDL); compiled with
various synthesis tools; and targeted for XC4000, Spartan, Spartan-II,
Spartan-XL, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and XC5200
devices. Xilinx equally endorses both Verilog and VHDL. VHDL may
be more difficult to learn than Verilog and usually requires more
explanation.
The design examples in this manual were created with Verilog and
VHSIC Hardware Description Language (VHDL); compiled with
various synthesis tools; and targeted for Spartan-II, Virtex, Virtex-E,
Virtex-II, Virtex-II Pro, and XC5200 devices. Xilinx equally endorses
both Verilog and VHDL. VHDL may be more difficult to learn than
Verilog and usually requires more explanation.
This manual does not address certain topics that are important when
creating HDL designs, such as the design environment; verification
techniques; constraining in the synthesis tool; test considerations; and
system verification. Refer to your synthesis tool’s reference manuals
and design methodology notes for additional information.
Before using this manual, you should be familiar with the operations
that are common to all Xilinx software tools.
Synthesis and Simulation Design Guide
iv Xilinx Development System
Manual Contents
This book contains the following chapters.
• Chapter 1, “Introduction,” provides a general overview of
designing Field Programmable Gate Arrays (FPGAs) with HDLs.
This chapter also includes installation requirements and instruc-
tions.
• Chapter 2, “Understanding High-Density Design Flow,”
provides synthesis and Xilinx implementation techniques to
increase design performance and utilization.
• Chapter 3, “General HDL Coding Styles,” includes HDL coding
hints and design examples to help you develop an efficient
coding style.
• Chapter 4, “Architecture Specific HDL Coding Styles for Spartan-
II, Virtex, Virtex-E, Virtex-II, and Virtex-II Pro,” includes coding
techniques to help you use the latest Xilinx devices.
• Chapter 5 “Virtex-II Pro Considerations,” highlights some of the
outstanding features of Xilinx Virtex-II Pro FPGAs.
• Chapter 6, “Simulating Your Design,” describes simulation
methods for verifying the function and timing of your designs.
Additional Resources
For additional information, go to http://support.xilinx.com. The
following table lists some of the resources you can access from this
Web site. You can also directly access these resources using the
provided URLs.
Resource Description/URL
Tutorials Tutorials covering Xilinx design flows, from design entry to verification
and debugging
http://support.xilinx.com/support/techsup/tutorials/index.htm
Answers
Database
Current listing of solution records for the Xilinx software tools
Search this database using the search function at
http://support.xilinx.com/support/searchtd.htm
Application
Notes
Descriptions of device-specific design techniques and approaches
http://support.xilinx.com/apps/appsweb.htm
About This Manual
Synthesis and Simulation Design Guide v
Data Book Pages from The Programmable Logic Data Book, which contains device-
specific information on Xilinx device characteristics, including readback,
boundary scan, configuration, length count, and debugging
http://support.xilinx.com/partinfo/databook.htm
Xcell Journals Quarterly journals for Xilinx programmable logic users
http://support.xilinx.com/xcell/xcell.htm
Technical Tips Latest news, design tips, and patch information for the Xilinx design
environment
http://support.xilinx.com/support/techsup/journals/index.htm
Resource Description/URL
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