没有合适的资源?快使用搜索试试~ 我知道了~
TPS552882-Q1-车规级.pdf
1.该资源内容由用户上传,如若侵权请联系客服进行举报
2.虚拟产品一经售出概不退款(资源遇到问题,请及时私信上传者)
2.虚拟产品一经售出概不退款(资源遇到问题,请及时私信上传者)
版权申诉
0 下载量 71 浏览量
2023-07-22
15:46:13
上传
评论
收藏 3.38MB PDF 举报
温馨提示
试读
44页
TPS552882-Q1-车规级.pdf
资源推荐
资源详情
资源评论
TPS552882-Q1 36V 16A 降压/升压转换器
1 特性
• 符合 AEC-Q100 标准:
– 器件温度等级 1:–40°C 至 +125°C 环境工作
温度范围
• 宽输入和输出电压范围
– 宽输入电压范围:2.7V 至 36V
– 宽输出电压范围:0.8V 至 22V
• 在整个负载范围内具有高效率
– V
IN
= 12V、V
OUT
= 20V 且 I
OUT
= 3A 时效率为
97%
• 避免频率干扰和串扰
– 可选的时钟同步
– 可编程开关频率范围为 200kHz 至 2.2MHz
• 降低 EMI
– 可选可编程扩展频谱
– 无引线封装
• 丰富的保护特性
– 输出过压保护
– 利用断续模式实现输出短路保护
– 热关断保护
– 可编程平均电感器电流限制高达 16A
• 小解决方案尺寸
– 开关频率高达 2.2MHz(最大值)
– 4.0mm × 3.5mm HotRod
™
QFN 封装
• 电缆上压降的可调输出电压补偿
• 轻负载状态下的可编程 PFM 和 FPWM 模式
• 感应电阻器的可编程输出电流限制
• ±1% 基准电压精度
• 固定 4ms 软启动时间
• 使用 TPS552882-Q1 并借助 WEBENCH
®
Power
Designer 创建定制设计方案
2 应用
• USB PD
• 汽车信息娱乐系统与仪表组
• 汽车充电器
3 说明
TPS552882-Q1 是一款同步四开关降压/升压转换器,
能够将输出电压稳定在等于、高于或低于输入电压的某
一电压值上。TPS552882-Q1 在 2.7V 至 36V 的宽输
入电压范围内工作,可输出 0.8V 至 22V 电压以支持各
种不同的应用。
TPS552882-Q1 集成了两个 16A MOSFET,其中的升
压腿可实现解决方案尺寸和效率间的平衡。
TPS552882-Q1 使用外部电阻分压器,通过 1.2V 内部
基准电压来设置输出电压。TPS552882-Q1 能够通过
12V 输入电压提供 100W 的功率。
TPS552882-Q1 采用平均电流模式控制方案。开关频
率可通过外部电阻在 200kHz 至 2.2MHz 之间进行编
程,并且可与外部时钟同步。TPS552882-Q1 还提供
可选的扩频,从而更大限度地减少峰值 EMI。
TPS552882-Q1 提供输出过压保护、平均电感器电流
限制、逐周期峰值电流限制和输出短路保护。
TPS552882-Q1 还使用持续过载情况下的可选输出电
流限制和断续模式保护来确保安全运行。
TPS552882-Q1 可以使用具有高开关频率的小型电感
器和电容器。此器件采用 4.0mm × 3.5mm QFN 封
装。
器件信息
器件型号
封装
(1)
封装尺寸
TPS552882-Q1 VQFN-HR 4.00mm × 3.50mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
DR1L
VIN
TPS552882-Q1
ILIM
VIN = 2.7V to 36V
MODE
C7
PGND
COMP
R5
R3
C2
VOUT
VOUT = 0.8V to 20V
C4
BOOT1
OFF
ON
C6
L1
4.7µH
SW2
BOOT2
DR1H
C1
AGND
C5
PG
VCC
C3
4.7µF
FSW
EN/UVLO
SW1
CDC
R4
DITH/SYNC
C8
R2
ISP
ISN
R7
10PŸ
0.1µF0.1µF
R8
FB
CC
R2
R1
典型应用电路
TPS552882-Q1
ZHCSMV3 – DECEMBER 2020
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSFQ8
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................ 9
7 Detailed Description......................................................12
7.1 Overview................................................................... 12
7.2 Functional Block Diagram......................................... 13
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................19
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
9 Power Supply Recommendations................................29
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 31
11 Device and Documentation Support..........................32
11.1 Device Support........................................................32
11.2 接收文档更新通知................................................... 32
11.3 支持资源..................................................................32
11.4 Trademarks............................................................. 32
11.5 术语表..................................................................... 32
11.6 静电放电警告...........................................................32
12 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
DATE REVISION NOTES
December 2020 * Initial release.
TPS552882-Q1
ZHCSMV3 – DECEMBER 2020
www.ti.com.cn
2 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS552882-Q1
5 Pin Configuration and Functions
CDC
AGND
PG
VIN
EN/UVLO
FSW
BOOT1
SW2
DR1H
ILIM
MODE
DR1L
BOOT2
VOUT
VCC
COMP
PGND
ISP
SW1
ISN
DITH/SYNC
SW2
PGND
VOUT
1
2
3
4
5
6
7
19
18
17
16
15
14
13
8
9
10
11
12
23
22
21
20
24
25
26
FB
CC
图 5-1. 26-pin VQFN-HR RPM Transparent (Top View)
表 5-1. Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 DR1L O Gate driver output for low-side MOSFET in buck side
2 DR1H O Gate driver output for high-side MOSFET in buck side
3 VIN PWR Power supply to the IC from input voltage
4 EN/UVLO I
Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high
level enables the device. Logic low level disables the device and turns it into shutdown mode. After
the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as
programmable UVLO input with 1.23-V internal reference.
5 PG O
Power good indication. When the output voltage is above 95% of the setting output voltage, this pin
outputs high impedance. When the output voltage is below 90% of the setting output voltage, this pin
outputs low level
6 CC O Constant current output indication
7 DITH/SYNC I
Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and
ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there is
no dithering function. An external clock can be applied at this pin to synchronize the switching
frequency.
8 FSW I The switching frequency is programmed by a resistor between this pin and the AGND pin.
9, 24 PGND PWR Power ground of the IC. It is connected to the source of the low-side MOSFET.
10 AGND PWR Signal ground of the IC
11, 26 VOUT PWR Output of the buck-boost converter
www.ti.com.cn
TPS552882-Q1
ZHCSMV3 – DECEMBER 2020
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS552882-Q1
表 5-1. Pin Functions (continued)
PIN
I/O DESCRIPTION
NO. NAME
12 ISP I
Positive input of the current sense amplifier. An optional current sense resistor connected between
the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current
limit setting value in the register, a slow constant current control loop becomes active and starts to
regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin
together with the VOUT pin can disable the output current limit function.
13 ISN I
Negative input of the current sense amplifier. An optional current sense resistor connected between
the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current
limit setting value in the register, a slow constant current control loop becomes active and starts to
regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin
together with the VOUT pin can disable the output current limit function.
14 FB I Connect to the center of a resistor divider to program the output voltage.
15 MODE I
Setting the operation modes of the TPS55288x to select PFM mode or forced PWM mode in light
load condition and to select the internal LDO or external 5 V for VCC by a resistor between this pin
and AGND.
16 CDC O
Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a
resistor between this pin and AGND to increase the output voltage to compensate voltage droop
across the cable caused by the cable resistance.
17 ILIM O
Average inductor current limit setting pin. Connect an external resistor between this pin and the
AGND pin.
18 COMP I
Output of the internal error amplifier. Connect the loop compensation network between this pin and
the AGND pin.
19 VCC O
Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this
pin and the AGND pin.
20 BOOT2 O
Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1 µF must be
connected between this pin and the SW2 pin.
21, 25 SW2 I
The switching node pin of the boost side. It is connected to the drain of the internal low-side power
MOSFET and the source of internal high-side power MOSFET.
22 BOOT1 I
Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1 µF must be
connected between this pin and the SW1 pin.
23 SW1 I
The switching node pin of the buck side. It is connected to the drain of the external low-side power
MOSFET and the source of external high-side power MOSFET.
TPS552882-Q1
ZHCSMV3 – DECEMBER 2020
www.ti.com.cn
4 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS552882-Q1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
Voltage range
at terminals
(2)
VIN, SW1
–0.3
40 V
DRH1, BOOT1
SW1–0.3
SW1+6 V
VCC, DRL1, PG, CC, ILIM, FSW, COMP, FB, MODE, CDC, DITH/
SYNC
–0.3
6 V
VOUT, SW2, ISP, ISN
–0.3
25 V
ISP, ISN VOUT-6 VOUT+6 V
EN -0.3 20 V
BOOT2
SW2–0.3
SW2+6 V
DRL1, CC, ILIM, FSW, COMP, FB, MODE, CDC, DITH/SYNC
–0.3
VCC+0.3 V
T
J
Operating Junction, T
J
(3)
–40
150 °C
T
stg
Storage temperature
–65
150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE UNIT
V
(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(2)
±2000
V
Charged-device model (CDM), per AEC Q100-011, all pins
(3)
±500
V
(ESD)
(1)
Electrostatic discharge Charged-device model (CDM), per AEC Q100-011, corner pins
(3)
±750 V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary
precautions.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary
precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
IN
Input voltage range 2.7 36 V
V
OUT
Output voltage range 0.8 22 V
L Effective inductance range 1 4.7 10 µH
C
IN
Effective input capacitance range 4.7 22 µF
C
OUT
Effective output capacitance range 10 100 1000 µF
T
J
Operating junction temperature
–40
150 °C
www.ti.com.cn
TPS552882-Q1
ZHCSMV3 – DECEMBER 2020
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS552882-Q1
剩余43页未读,继续阅读
资源评论
RedCar
- 粉丝: 26
- 资源: 1764
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功