JEDEC Standard No. 230F.01
-i-
NAND FLASH INTERFACE INTEROPERABILITY
Contents
Pages
1
Scope ........................................................................................................................... 1
2
Terms, Definitions, Abbreviations, and Conventions ........................................................ 1
2.1
Terms and Definitions ...................................................................................................... 1
2.2 Abbreviations .................................................................................................................. 3
2.3 Conventions .................................................................................................................... 3
2.3.2 Signal Names ................................................................................................................. 3
2.3.3 Precedence in Case of Conflict ....................................................................................... 3
2.4 Keywords ........................................................................................................................ 4
2.5 Byte, Word, and Dword Relationships ............................................................................. 4
2.6 Pin Description ................................................................................................................ 5
3
NAND Interface General Information .............................................................................. 8
3.1 NAND Interface Spec Overview ...................................................................................... 8
3.2 Supported Features and Operating Conditions Versus Data Transfer Rate ................... 9
3.3 Supported VrefQ Versus Data Transfer Rate ............................................................... 10
4
Physical Interface .......................................................................................................... 11
4.1 Input Specifications ....................................................................................................... 11
4.1.1 AC/DC Levels ............................................................................................................... 11
4.1.2 NAND DQ Rx Mask Specifications ............................................................................... 17
4.1.3 Controller DQ Rx Mask Specifications .......................................................................... 18
4.1.4 Vcent_DQ (pin_mid) Definition ..................................................................................... 19
4.1.5 CTT and LTT Interface (1.2 V VccQ) VIHL_AC Definition ............................................ 20
4.1.6 NAND Minimum Internal VrefQ Allowable Range ......................................................... 21
4.2 Output Specifications .................................................................................................... 22
4.2.1 Output Drive and ODT Strengths .................................................................................. 22
4.2.2 Output Levels for Unterminated Single-Ended DQ-Related Signals ............................. 26
4.2.3 Output Timing Reference Loads ................................................................................... 26
4.2.4 Single-Ended Output Slew Rate ................................................................................... 27
4.2.5 AC Differential Cross-Point ........................................................................................... 28
4.2.6 Output Specifications for R/B# Signal ........................................................................... 28
4.3 AC Overshoot/Undershoot Requirements .................................................................... 29
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