iv
3.5.1. Discovery without CE_n pin reduction ..................................................................... 77
3.5.2. Discovery with CE_n pin reduction .......................................................................... 78
3.5.3. Target Initialization ................................................................................................... 81
4. Data Interface and Timing ...................................................................................................... 82
4.1. Data Interface Type Overview ........................................................................................ 82
4.2. Signal Function Assignment............................................................................................ 82
4.3. Bus State ......................................................................................................................... 83
4.3.1. SDR.......................................................................................................................... 83
4.3.2. NV-DDR ................................................................................................................... 84
4.3.3. NV-DDR2 ................................................................................................................. 85
4.3.4. Pausing Data Input/Output ...................................................................................... 85
4.4. NV-DDR / NV-DDR2 and Repeat Bytes ......................................................................... 86
4.5. Data Interface / Timing Mode Transitions ....................................................................... 86
4.5.1. SDR Transition from NV-DDR or NV-DDR2 ............................................................ 86
4.5.2. NV-DDR2 Recommendations .................................................................................. 87
4.6. Test Conditions ............................................................................................................... 87
4.6.1. SDR Only ................................................................................................................. 87
4.6.2. Devices that Support Driver Strength Settings ........................................................ 88
4.7. I/O Drive Strength ........................................................................................................... 88
4.8. Output Slew Rate ............................................................................................................ 89
4.9. Capacitance .................................................................................................................... 93
4.9.1. Capacitance Requirements (Informative) ................................................................ 95
4.10. Impedance Values ....................................................................................................... 97
4.10.1. NV-DDR ............................................................................................................... 98
4.10.2. NV-DDR2 ........................................................................................................... 100
4.11. Input Slew Rate Derating .......................................................................................... 100
4.11.1. NV-DDR ............................................................................................................. 101
4.11.2. NV-DDR2 ........................................................................................................... 101
4.12. Differential Signaling (NV-DDR2) .............................................................................. 108
4.13. Warmup Cycles (NV-DDR2) ...................................................................................... 109
4.14. On-die Termination (NV-DDR2) ................................................................................ 110
4.14.1. Self-termination ODT.......................................................................................... 111
4.14.2. Matrix Termination .............................................................................................. 112
4.15. Timing Parameters .................................................................................................... 119
4.15.1. General Parameters ........................................................................................... 120
4.15.2. SDR .................................................................................................................... 122
4.15.3. NV-DDR ............................................................................................................. 123
4.15.4. NV-DDR2 ........................................................................................................... 124
4.16. Timing Modes ............................................................................................................ 125
4.16.1. SDR .................................................................................................................... 125
4.16.2. NV-DDR ............................................................................................................. 127
4.16.3. NV-DDR2 ........................................................................................................... 130
4.17. Timing Diagrams ....................................................................................................... 135
4.17.1. SDR .................................................................................................................... 135
4.17.2. NV-DDR ............................................................................................................. 143
4.17.3. NV-DDR2 ........................................................................................................... 154
5. Command Definition ............................................................................................................. 160
5.1. Command Set ............................................................................................................... 160
5.2. Command Descriptions ................................................................................................. 163
5.3. Reset Definition ............................................................................................................. 167
5.4. Synchronous Reset Definition ....................................................................................... 167
5.5. Reset LUN Definition ..................................................................................................... 168
5.6. Read ID Definition ......................................................................................................... 169
5.7. Read Parameter Page Definition .................................................................................. 173
5.7.1. Parameter Page Data Structure Definition ............................................................ 175
5.7.2. Extended Parameter Page Data Structure Definition ............................................ 192
