Open NAND Flash Interface Specification
Revision 2.0
27-February-2008
Hynix Semiconductor
Intel Corporation
Micron Technology, Inc.
Phison Electronics Corp.
Sony Corporation
Spansion
STMicroelectronics
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This 2.0 revision of the Open NAND Flash Interface specification ("Final Specification") is
available for download at www.onfi.org.
SPECIFICATION DISCLAIMER
THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS
SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF
ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMNETATION OF INFORMATION
IN THIS SPECIFICATION. THE AUTHORS DO NOT WARRANT OR REPRESENT THAT SUCH
USE WILL NOT INFRINGE SUCH RIGHTS. THE PROVISION OF THIS SPECIFICATION TO
YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
Copyright 2005-2008, Hynix Semiconductor, Intel Corporation, Micron Technology, Inc., Phison
Electronics Corp., Sony Corporation, Spansion, STMicroelectronics. All rights reserved.
For more information about ONFI, refer to the ONFI Workgroup website at www.onfi.org.
All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
ONFI Workgroup Technical Editor:
Amber Huffman
Intel Corporation
2111 NE 25th Ave M/S JF2-53
Hillsboro, OR 97124 USA
Tel: (503) 264-7929
Email: [email protected]
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Table of Contents
1. Introduction ........................................................................................................................... 1
1.1. Goals and Objectives........................................................................................................ 1
1.2. References........................................................................................................................ 1
1.3. Definitions, abbreviations, and conventions...................................................................... 1
1.3.1. Definitions and Abbreviations .................................................................................... 1
1.3.2. Conventions............................................................................................................... 4
2. Physical Interface ................................................................................................................. 7
2.1. TSOP-48 and WSOP-48 Pin Assignments....................................................................... 7
2.2. LGA-52 Pad Assignments............................................................................................... 10
2.3. BGA-63 Ball Assignments............................................................................................... 11
2.4. BGA-100 Ball Assignments............................................................................................. 15
2.5. Signal Descriptions ......................................................................................................... 19
2.6. CE# Signal Requirements............................................................................................... 24
2.6.1. Source Synchronous Data Interface Requirements ................................................ 24
2.7. Absolute Maximum DC Ratings ...................................................................................... 24
2.8. Recommended DC Operating Conditions....................................................................... 25
2.8.1. I/O Power (VccQ) and I/O Ground (VssQ)............................................................... 25
2.9. AC Overshoot/Undershoot Requirements ...................................................................... 25
2.10. DC and Operating Characteristics............................................................................... 26
2.11. Calculating Pin Capacitance ....................................................................................... 28
2.12. Staggered Power-up.................................................................................................... 28
2.13. Independent Data Buses............................................................................................. 29
2.14. Bus Width Requirements............................................................................................. 30
2.15. Ready/Busy (R/B#) Requirements .............................................................................. 30
2.15.1. Power-On Requirements...................................................................................... 30
2.15.2. R/B# and SR[6] Relationship ............................................................................... 31
2.16. Write Protect................................................................................................................ 31
3. Memory Organization ......................................................................................................... 32
3.1. Addressing ......................................................................................................................33
3.1.1. Interleaved Addressing ............................................................................................ 34
3.1.2. Logical Unit Selection .............................................................................................. 34
3.1.3. Multiple LUN Operation Restrictions........................................................................ 34
3.2. Factory Defect Mapping.................................................................................................. 35
3.2.1. Device Requirements............................................................................................... 35
3.2.2. Host Requirements .................................................................................................. 35
3.3. Discovery and Initialization.............................................................................................. 36
3.3.1. CE# Discovery ......................................................................................................... 36
3.3.2. Target Initialization................................................................................................... 37
3.4. Partial Page Programming.............................................................................................. 38
3.4.1. Requirements........................................................................................................... 38
3.4.2. Host Discovery......................................................................................................... 38
4. Data Interface and Timing .................................................................................................. 39
4.1. Data Interface Types....................................................................................................... 39
4.1.1. Signal Function Reassignment................................................................................ 39
4.1.2. Bus State ................................................................................................................. 40
4.1.3. Source Synchronous and Repeat Bytes.................................................................. 41
4.1.4. Data Interface / Timing Mode Transitions................................................................ 42
4.2. Timing Parameters.......................................................................................................... 43
4.2.1. General Timings....................................................................................................... 43
4.2.2. Asynchronous .......................................................................................................... 44
4.2.3. Source Synchronous................................................................................................ 49
4.3. Timing Diagrams............................................................................................................. 60
4.3.1. Asynchronous .......................................................................................................... 60
4.3.2. Source Synchronous................................................................................................ 67
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4.4. Command Examples....................................................................................................... 76
4.4.1. Asynchronous .......................................................................................................... 76
4.4.2. Source Synchronous................................................................................................ 79
5. Command Definition ........................................................................................................... 84
5.1. Command Set ................................................................................................................. 84
5.2. Command Descriptions................................................................................................... 86
5.3. Reset Definition............................................................................................................... 89
5.4. Synchronous Reset Definition......................................................................................... 89
5.5. Read ID Definition........................................................................................................... 90
5.6. Read Parameter Page Definition .................................................................................... 91
5.6.1. Parameter Page Data Structure Definition .............................................................. 94
5.7. Read Unique ID Definition............................................................................................. 106
5.8. Block Erase Definition................................................................................................... 108
5.9. Read Status Definition .................................................................................................. 108
5.10. Read Status Enhanced Definition ............................................................................. 109
5.11. Read Status and Read Status Enhanced required usage ........................................ 109
5.12. Status Field Definition................................................................................................ 110
5.13. Read Definition.......................................................................................................... 111
5.14. Read Cache Definition............................................................................................... 113
5.15. Page Program Definition ........................................................................................... 117
5.16. Page Cache Program Definition................................................................................ 119
5.17. Copyback Definition................................................................................................... 122
5.18. Change Read Column Definition............................................................................... 127
5.19. Change Write Column Definition ............................................................................... 127
5.20. Set Features Definition.............................................................................................. 128
5.21. Get Features Definition.............................................................................................. 130
5.22. Feature Parameter Definitions .................................................................................. 130
5.22.1. Timing Mode....................................................................................................... 131
5.22.2. I/O Drive Strength............................................................................................... 131
6. Interleaved Operations ..................................................................................................... 133
6.1. Requirements................................................................................................................ 133
6.2. Status Register Behavior .............................................................................................. 134
6.3. Interleaved Page Program ............................................................................................ 134
6.4. Interleaved Copyback Program .................................................................................... 137
6.5. Interleaved Block Erase ................................................................................................ 139
7. Behavioral Flows .............................................................................................................. 140
7.1. Target behavioral flows................................................................................................. 140
7.1.1. Variables................................................................................................................ 140
7.1.2. Idle states............................................................................................................... 140
7.1.3. Idle Read states..................................................................................................... 142
7.1.4. Reset command states .......................................................................................... 143
7.1.5. Read ID command states ...................................................................................... 144
7.1.6. Read Parameter Page command states................................................................ 145
7.1.7. Read Unique ID command states.......................................................................... 147
7.1.8. Page Program and Page Cache Program command states ................................. 147
7.1.9. Block Erase command states ................................................................................ 149
7.1.10. Read command states ....................................................................................... 151
7.1.11. Set Features command states ........................................................................... 153
7.1.12. Get Features command states........................................................................... 154
7.1.13. Read Status command states............................................................................ 154
7.1.14. Read Status Enhanced command states........................................................... 155
7.2. LUN behavioral flows .................................................................................................... 156
7.2.1. Variables................................................................................................................ 156
7.2.2. Idle command states.............................................................................................. 156
7.2.3. Idle Read states..................................................................................................... 158
7.2.4. Status states .......................................................................................................... 158
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7.2.5. Reset states ........................................................................................................... 160
7.2.6. Block Erase command states ................................................................................ 160
7.2.7. Read command states........................................................................................... 162
7.2.8. Page Program and Page Cache Program command states ................................. 163
A. Sample Code for CRC-16 (Informative) ........................................................................... 167
B. Spare Size Recommendations (Informative).................................................................... 169
