/*
* The Clear BSD License
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_enet.h"
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
#include "fsl_cache.h"
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.enet"
#endif
/*! @brief IPv4 PTP message IP version offset. */
#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU
/*! @brief IPv4 PTP message UDP protocol offset. */
#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U
/*! @brief IPv4 PTP message UDP port offset. */
#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U
/*! @brief IPv4 PTP message UDP message type offset. */
#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU
/*! @brief IPv4 PTP message UDP version offset. */
#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU
/*! @brief IPv4 PTP message UDP clock id offset. */
#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU
/*! @brief IPv4 PTP message UDP sequence id offset. */
#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U
/*! @brief IPv4 PTP message UDP control offset. */
#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU
/*! @brief IPv6 PTP message UDP protocol offset. */
#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U
/*! @brief IPv6 PTP message UDP port offset. */
#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U
/*! @brief IPv6 PTP message UDP message type offset. */
#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU
/*! @brief IPv6 PTP message UDP version offset. */
#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU
/*! @brief IPv6 PTP message UDP clock id offset. */
#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U
/*! @brief IPv6 PTP message UDP sequence id offset. */
#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU
/*! @brief IPv6 PTP message UDP control offset. */
#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU
/*! @brief PTPv2 message Ethernet packet type offset. */
#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU
/*! @brief PTPv2 message Ethernet message type offset. */
#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU
/*! @brief PTPv2 message Ethernet version type offset. */
#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU
/*! @brief PTPv2 message Ethernet clock id offset. */
#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22
/*! @brief PTPv2 message Ethernet sequence id offset. */
#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c
/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */
#define ENET_ETHERNETL2 0x88F7U
/*! @brief Packet type IPv4. */
#define ENET_IPV4 0x0800U
/*! @brief Packet type IPv6. */
#define ENET_IPV6 0x86ddU
/*! @brief Packet type VLAN. */
#define ENET_8021QVLAN 0x8100U
/*! @brief UDP protocol type. */
#define ENET_UDPVERSION 0x0011U
/*! @brief Packet IP version IPv4. */
#define ENET_IPV4VERSION 0x0004U
/*! @brief Packet IP version IPv6. */
#define ENET_IPV6VERSION 0x0006U
/*! @brief Ethernet mac address length. */
#define ENET_FRAME_MACLEN 6U
/*! @brief Ethernet VLAN header length. */
#define ENET_FRAME_VLAN_TAGLEN 4U
/*! @brief MDC frequency. */
#define ENET_MDC_FREQUENCY 2500000U
/*! @brief NanoSecond in one second. */
#define ENET_NANOSECOND_ONE_SECOND 1000000000U
/*! @brief Define a common clock cycle delays used for time stamp capture. */
#ifndef ENET_1588TIME_DELAY_COUNT
#define ENET_1588TIME_DELAY_COUNT 10U
#endif
/*! @brief Defines the macro for converting constants from host byte order to network byte order. */
#define ENET_HTONS(n) __REV16(n)
#define ENET_HTONL(n) __REV(n)
#define ENET_NTOHS(n) __REV16(n)
#define ENET_NTOHL(n) __REV(n)
/*! @brief Define the ENET ring/class bumber . */
enum _enet_ring_number
{
kENET_Ring0 = 0U, /*!< ENET ring/class 0. */
#if FSL_FEATURE_ENET_QUEUE > 1
kENET_Ring1 = 1U, /*!< ENET ring/class 1. */
kENET_Ring2 = 2U /*!< ENET ring/class 2. */
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
};
/*! @brief Define interrupt IRQ handler. */
#if FSL_FEATURE_ENET_QUEUE > 1
typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
uint32_t ENET_GetInstance(ENET_Type *base);
/*!
* @brief Set ENET MAC controller with the configuration.
*
* @param base ENET peripheral base address.
* @param handle The ENET handle pointer.
* @param config ENET Mac configuration.
* @param bufferConfig ENET buffer configuration.
* @param macAddr ENET six-byte mac address.
* @param srcClock_Hz ENET module clock source, normally it's system clock.
*/
static void ENET_SetMacController(ENET_Type *base,
enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig,
uint8_t *macAddr,
uint32_t srcClock_Hz);
/*!
* @brief Set ENET handler.
*
* @param base ENET peripheral base address.
* @param handle The ENET handle pointer.
* @param config ENET configuration stucture pointer.
* @param bufferConfig ENET buffer configuration.
*/
static void ENET_SetHandler(ENET_Type *base,
enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig);
/*!
* @brief Set ENET MAC transmit buffer descriptors.
*
* @param handle The ENET handle pointer.
* @param config The ENET configuration structure.
* @param bufferConfig The ENET b
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NXP i.MX RT1052实现SD卡读写数据【支持RT105X系列控制器_库函数驱动】.zip
共248个文件
h:111个
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i:16个
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NXP i.MX RT1052驱动程序,库函数驱动。 支持RT105X系列控制器编译和运行。 项目代码可顺利编译运行~
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NXP i.MX RT1052实现SD卡读写数据【支持RT105X系列控制器_库函数驱动】.zip (248个子文件)
fsl_enet.c 110KB
fsl_mmc.c 91KB
fsl_sai.c 78KB
fsl_edma.c 75KB
tftlcd.c 73KB
fsl_trng.c 72KB
fsl_flexcan.c 71KB
fsl_usdhc.c 63KB
fsl_lpi2c.c 61KB
fsl_lpspi.c 61KB
fsl_lpuart.c 60KB
fsl_sd.c 58KB
fsl_str.c 43KB
fsl_semc.c 36KB
fsl_lpspi_edma.c 36KB
fsl_dcp.c 36KB
fsl_sdio.c 35KB
fsl_flexio_spi.c 35KB
fsl_clock.c 31KB
fsl_flexio_i2c_master.c 30KB
fsl_flexspi.c 29KB
fsl_io.c 27KB
fsl_flexio_uart.c 26KB
fsl_pwm.c 26KB
fsl_flexio_i2s.c 25KB
fsl_spdif.c 22KB
fsl_snvs_lp.c 21KB
fsl_shell.c 21KB
fsl_csi.c 21KB
fsl_spdif_edma.c 20KB
fsl_pxp.c 19KB
fsl_lpi2c_edma.c 18KB
fsl_log.c 18KB
fsl_cache.c 17KB
fsl_sai_edma.c 17KB
elcdif.c 16KB
fsl_enc.c 16KB
touch.c 16KB
fsl_qtmr.c 15KB
usmart.c 15KB
fsl_flexio_spi_edma.c 15KB
fsl_adc_etc.c 15KB
fsl_sdmmc_host.c 15KB
fsl_snvs_hp.c 14KB
fsl_sdmmc_host.c 14KB
fsl_flexio_i2s_edma.c 14KB
fsl_lpuart_edma.c 12KB
fsl_flexio_uart_edma.c 12KB
fsl_dcdc.c 12KB
usmart_str.c 12KB
w25qxx.c 11KB
fsl_lpuart_freertos.c 11KB
fsl_debug_console.c 11KB
fsl_flexio.c 11KB
fsl_elcdif.c 11KB
gt9147.c 10KB
system_MIMXRT1052.c 10KB
fsl_sdmmc_host.c 10KB
fsl_adc.c 10KB
fsl_sdmmc_common.c 10KB
fsl_xbara.c 10KB
fsl_cmp.c 9KB
ft5206.c 9KB
sys.c 9KB
fsl_notifier.c 8KB
fsl_tsc.c 8KB
fsl_flexram.c 8KB
24l01.c 8KB
sdram.c 8KB
fsl_kpp.c 7KB
fsl_bee.c 7KB
fsl_aoi.c 7KB
fsl_common.c 6KB
delay.c 6KB
lpuart.c 6KB
main.c 6KB
fsl_gpio.c 6KB
fsl_sdmmc_event.c 5KB
malloc.c 5KB
fsl_sdmmc_event.c 5KB
fsl_sdmmc_event.c 5KB
fsl_wdog.c 5KB
fsl_pit.c 5KB
ott2001a.c 5KB
fsl_gpt.c 5KB
fsl_ewm.c 5KB
fsl_xbarb.c 4KB
fsl_swo.c 4KB
24cxx.c 4KB
fsl_lpi2c_freertos.c 4KB
fsl_rtwdog.c 4KB
fsl_lpspi_freertos.c 4KB
fsl_dmamux.c 4KB
lpspi.c 4KB
fsl_gpc.c 4KB
ctiic.c 4KB
usdhc1_sdcard.c 3KB
key.c 3KB
fsl_aipstz.c 3KB
fsl_pmu.c 3KB
共 248 条
- 1
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- 3
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