NXP i.MX RT1052驱动触摸屏【支持RT105X系列控制器_库函数驱动】.zip

/* * The Clear BSD License * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "fsl_enet.h" #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL #include "fsl_cache.h" #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ /******************************************************************************* * Definitions ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.enet" #endif /*! @brief IPv4 PTP message IP version offset. */ #define ENET_PTP1588_IPVERSION_OFFSET 0x0EU /*! @brief IPv4 PTP message UDP protocol offset. */ #define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U /*! @brief IPv4 PTP message UDP port offset. */ #define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U /*! @brief IPv4 PTP message UDP message type offset. */ #define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU /*! @brief IPv4 PTP message UDP version offset. */ #define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU /*! @brief IPv4 PTP message UDP clock id offset. */ #define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU /*! @brief IPv4 PTP message UDP sequence id offset. */ #define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U /*! @brief IPv4 PTP message UDP control offset. */ #define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU /*! @brief IPv6 PTP message UDP protocol offset. */ #define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U /*! @brief IPv6 PTP message UDP port offset. */ #define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U /*! @brief IPv6 PTP message UDP message type offset. */ #define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU /*! @brief IPv6 PTP message UDP version offset. */ #define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU /*! @brief IPv6 PTP message UDP clock id offset. */ #define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U /*! @brief IPv6 PTP message UDP sequence id offset. */ #define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU /*! @brief IPv6 PTP message UDP control offset. */ #define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU /*! @brief PTPv2 message Ethernet packet type offset. */ #define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU /*! @brief PTPv2 message Ethernet message type offset. */ #define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU /*! @brief PTPv2 message Ethernet version type offset. */ #define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU /*! @brief PTPv2 message Ethernet clock id offset. */ #define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 /*! @brief PTPv2 message Ethernet sequence id offset. */ #define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c /*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ #define ENET_ETHERNETL2 0x88F7U /*! @brief Packet type IPv4. */ #define ENET_IPV4 0x0800U /*! @brief Packet type IPv6. */ #define ENET_IPV6 0x86ddU /*! @brief Packet type VLAN. */ #define ENET_8021QVLAN 0x8100U /*! @brief UDP protocol type. */ #define ENET_UDPVERSION 0x0011U /*! @brief Packet IP version IPv4. */ #define ENET_IPV4VERSION 0x0004U /*! @brief Packet IP version IPv6. */ #define ENET_IPV6VERSION 0x0006U /*! @brief Ethernet mac address length. */ #define ENET_FRAME_MACLEN 6U /*! @brief Ethernet VLAN header length. */ #define ENET_FRAME_VLAN_TAGLEN 4U /*! @brief MDC frequency. */ #define ENET_MDC_FREQUENCY 2500000U /*! @brief NanoSecond in one second. */ #define ENET_NANOSECOND_ONE_SECOND 1000000000U /*! @brief Define a common clock cycle delays used for time stamp capture. */ #ifndef ENET_1588TIME_DELAY_COUNT #define ENET_1588TIME_DELAY_COUNT 10U #endif /*! @brief Defines the macro for converting constants from host byte order to network byte order. */ #define ENET_HTONS(n) __REV16(n) #define ENET_HTONL(n) __REV(n) #define ENET_NTOHS(n) __REV16(n) #define ENET_NTOHL(n) __REV(n) /*! @brief Define the ENET ring/class bumber . */ enum _enet_ring_number { kENET_Ring0 = 0U, /*!< ENET ring/class 0. */ #if FSL_FEATURE_ENET_QUEUE > 1 kENET_Ring1 = 1U, /*!< ENET ring/class 1. */ kENET_Ring2 = 2U /*!< ENET ring/class 2. */ #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ }; /*! @brief Define interrupt IRQ handler. */ #if FSL_FEATURE_ENET_QUEUE > 1 typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); /******************************************************************************* * Prototypes ******************************************************************************/ /*! * @brief Get the ENET instance from peripheral base address. * * @param base ENET peripheral base address. * @return ENET instance. */ uint32_t ENET_GetInstance(ENET_Type *base); /*! * @brief Set ENET MAC controller with the configuration. * * @param base ENET peripheral base address. * @param handle The ENET handle pointer. * @param config ENET Mac configuration. * @param bufferConfig ENET buffer configuration. * @param macAddr ENET six-byte mac address. * @param srcClock_Hz ENET module clock source, normally it's system clock. */ static void ENET_SetMacController(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig, uint8_t *macAddr, uint32_t srcClock_Hz); /*! * @brief Set ENET handler. * * @param base ENET peripheral base address. * @param handle The ENET handle pointer. * @param config ENET configuration stucture pointer. * @param bufferConfig ENET buffer configuration. */ static void ENET_SetHandler(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); /*! * @brief Set ENET MAC transmit buffer descriptors. * * @param handle The ENET handle pointer. * @param config The ENET configuration structure. * @param bufferConfig The ENET b