FPGA PGL22G实现基于OV5640的以太网视频传输【Verilog HDL驱动】.zip

Clock Regions-Block Scope: +--------------------------------------------------------------------------+ | (X0,Y*): (Xmin,Xmax,Ymin,Ymax) | (X1,Y*): (Xmin,Xmax,Ymin,Ymax) +--------------------------------------------------------------------------+ | (X0,Y2): (0,39,60,89) | (X1,Y2): (40,75,60,89) | (X0,Y1): (0,39,30,59) | (X1,Y1): (40,75,30,59) | (X0,Y0): (0,39,0,29) | (X1,Y0): (40,75,0,29) +--------------------------------------------------------------------------+ Clock Regions-Clock Primitives: +--------------------------------------------------------------------------------------------------------------------------------------+ | Clock Region Name | CLK PAD | PLL PAD | RCKB | IOCKGATE | IOCKDIV | CLMA | CLMS | DRM | APM +--------------------------------------------------------------------------------------------------------------------------------------+ | (X0,Y0) | 4 | 6 | 4 | 2 | 2 | 520 | 180 | 12 | 0 | (X0,Y1) | 4 | 6 | 4 | 2 | 2 | 610 | 210 | 12 | 0 | (X0,Y2) | 4 | 6 | 4 | 2 | 2 | 524 | 180 | 6 | 0 | (X1,Y0) | 4 | 6 | 4 | 2 | 2 | 450 | 150 | 6 | 10 | (X1,Y1) | 4 | 6 | 4 | 2 | 2 | 540 | 180 | 6 | 10 | (X1,Y2) | 4 | 6 | 4 | 2 | 2 | 630 | 210 | 6 | 10 +--------------------------------------------------------------------------------------------------------------------------------------+ Global Clock Buffer Constraint Details: +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Clock Region Of Buffer Site | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | u_eth_top/u_gmii_to_rgmii/u_rgmii_rx/U_pll_phase_shift/u_pll_e1/goppll | CLKOUT0 | eth_rx_clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | --- | --- | (72,74,18,25) | (39,39,16,16) | 879 | 0 | u_clk_wiz_0/u_pll_e1/goppll | CLKOUT0 | clk_50m | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | --- | --- | --- | --- | 6 | 0 | u_eth_top/u_gmii_to_rgmii/u_rgmii_rx/U_pll_phase_shift/u_pll_e1/goppll | CLKOUT1 | u_eth_top/u_gmii_to_rgmii/gmii_tx_clk_deg | CLK | clkbufg_2/gopclkbufg | CLKOUT | ntclkbufg_2 | --- | --- | (74,74,20,20) | --- | 1 | 0 | cam_pclk_ibuf/opit_1 | OUT | nt_cam_pclk | CLK | cam_pclkbufg/gopclkbufg | CLKOUT | cam_pclk_g | --- | --- | --- | --- | 128 | 0 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Global Clock Source Constraint Details: +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Load Net | Clock Region Of Source Site | Source Site | Clock Buffer Loads | Non-Clock Buffer Loads +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | u_eth_top/u_gmii_to_rgmii/u_rgmii_rx/U_pll_phase_shift/u_pll_e1/goppll | CLKOUT0 | eth_rx_clk | (X0,Y0) | PLL_82_71 | 1 | 0 | u_clk_wiz_0/u_pll_e1/goppll | CLKOUT0 | clk_50m | (X0,Y2) | PLL_82_319 | 1 | 0 | u_eth_top/u_gmii_to_rgmii/u_rgmii_rx/U_pll_phase_shift/u_pll_e1/goppll | CLKOUT1 | u_eth_top/u_gmii_to_rgmii/gmii_tx_clk_deg | (X0,Y0) | PLL_82_71 | 1 | 0 | cam_pclk_ibuf/opit_1 | OUT | nt_cam_pclk | (X0,Y2) | IOL_7_266 | 1 | 0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Device Cell Placement Summary for Global Clock Buffer: +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads +-----------