axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"
axi_vip_pkg.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/4fba"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"
axi_vip_if.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshared/798b/hdl"incdir="$ref_dir/../../../../vdma_lcd.srcs/sources_1/bd/design_1/ipshar
FPGA MPSoC_XCZU4EV实现PS通过VDMA驱动LCD显示（VITIS实现）.zip （2000个子文件） 
__synthesis_is_complete__ 0B libxil.a 5.59MB libxil.a 4.69MB libxil.a 2.7MB libxil.a 2.7MB libgcc.a 1.73MB libc.a 1.02MB libxilsecure.a 587KB libxilsecure.a 586KB libxilskey.a 576KB libm.a 576KB libxilpm.a 573KB libxilfpga.a 295KB libxilffs.a 48KB libgloss.a 22KB .analytics 712B assumedExternalFilesCache 4B runme.bat 229B runme.bat 229B design_1.bd 42KB bd_afc3.bd 38KB bd_afc3.bd 38KB design_1_wrapper.bif 225B design_1_wrapper.bit 7.44MB design_1_wrapper.bit 7.44MB design_1_wrapper.bit 7.44MB design_1_wrapper.bit 7.44MB design_1_wrapper.bit 7.44MB design_1.bxml 8KB bd_afc3.bxml 6KB ffunicode.c 1.87MB psu_init.c 679KB psu_init.c 679KB psu_init.c 679KB psu_init.c 679KB psu_init_gpl.c 678KB psu_init_gpl.c 678KB psu_init_gpl.c 678KB ff.c 223KB xfsbl_ddr_init.c 214KB xilskey_eps_zynqmp.c 102KB xvtc.c 85KB xvtc.c 85KB xvtc.c 85KB xilfpga_pcap.c 75KB pm_clock.c 70KB xsysmonpsu.c 69KB xsysmonpsu.c 69KB xsysmonpsu.c 69KB pm_api_sys.c 64KB xaxipmon.c 63KB xaxipmon.c 63KB xaxipmon.c 63KB pm_core.c 60KB pm_ddr.c 58KB xfsbl_initialization.c 56KB xfsbl_partition_load.c 52KB pm_reset.c 49KB xsecure.c 48KB xsecure.c 48KB xsecure_aes.c 46KB xsecure_aes.c 46KB xilskey_utils.c 43KB xaxivdma_channel.c 42KB xaxivdma_channel.c 42KB xaxivdma_channel.c 42KB xzdma.c 41KB xzdma.c 41KB xzdma.c 41KB xresetps.c 40KB xresetps.c 40KB xresetps.c 40KB xfsbl_qspi.c 40KB xaxivdma.c 39KB xaxivdma.c 39KB xaxivdma.c 39KB xscugic.c 38KB xscugic.c 38KB xilskey_eps_zynqmp_puf.c 37KB xclockps_mux.c 35KB xclockps_mux.c 35KB xclockps_mux.c 35KB pm_power.c 34KB xfsbl_plpartition_valid.c 33KB xfsbl_handoff.c 32KB xcsudma.c 32KB xcsudma.c 32KB xcsudma.c 32KB pm_cfg_obj.c 31KB pm_pinctrl.c 30KB pm_periph.c 30KB pm_master.c 29KB xgpiops.c 28KB xgpiops.c 28KB xgpiops.c 28KB pm_proc.c 28KB xclockps.c 27KB xclockps.c 27KB xclockps.c 27KB xgpiops_intr.c 27KB共 2000 条
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