AHB总线设计

WISHBONE - AHB BRIDGE

Table of Contents

Authors........................................................................................................................................2

Copyright & License....................................................................................................................2

Revision No. ...............................................................................................................................2

Disclaimer....................................................................................................................................2

Introduction..................................................................................................................................3

Limitations of Design..................................................................................................................3

Synthesizability............................................................................................................................3

Inserted by AHB Slave...........................................................................................................8

Inserted by Wishbone Master.................................................................................................9

Read with wait states.................................................................................................................10

Inserted by AHB Slave.........................................................................................................10

Inserted by Wishbone Master...............................................................................................11

Read after Write :.......................................................................................................................12

Write after Read :.......................................................................................................................13

References..................................................................................................................................15

Authors

TooMuch Semiconductor Solutions (info@toomuchsemi.com)

statement is not removed from the file and that any derivative work contains the original

copyright notice and the associated disclaimer.

This software is provided “as is” and without any express or implied warranties, including,

but not limited to, the implied warranties of merchantability and fitness for a particular

purpose. in no event shall the author or contributors be liable for any direct, indirect,

incidental, special, exemplary, or consequential damages (including, but not limited to,

procurement of substitute goods or services; loss of use, data, or profits; or business

interruption) however caused and on any theory of liability, whether in contract, strict

liability, or tort (including negligence or otherwise) arising in any way out of the use of this

software, even if advised of the possibility of such damage.

● Word size is 32 bits. It can be modified as per requirement.

● All transfers has been considered as non-sequential type.

Synthesizability

This code is completely synthesizable. The only care that has to be taken is that the AHB

clock(hclk) and reset(hresetn) signals have been left unconnnected inside the design. The

whole design is working on Wishbone clock and reset signals that should be provided by

Wishbone master.

Port Definations

Black Box

BRIDGE

clk_i

rst_i

cyc_i

stb_i

ack_o

data_o

data_i

addr_i

we_i

hready

hresp

htrans

hsel

hburst