AHB总线下的slave ram的verilog代码.pdf
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2020-07-27
22:56:56
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module ram_top(
hclk ,
hresetn ,
hsel_s ,
haddr_s ,
hburst_s ,
htrans_s ,
hrdata_s ,
hwdata_s ,
hwrite_s ,
hready_s ,
hresp_s
);
input hclk ;
input hresetn ;
input hsel_s ;
input [19:0] haddr_s ;
input [2:0] hburst_s ;
input [1:0] htrans_s ;
input [31:0] hwdata_s ;
input hwrite_s ;
output [1:0] hresp_s ;
output [31:0] hrdata_s ;
output hready_s ;
wire [31:0] ram_rdata ;
wire [17:0] ram_addr ;
wire [31:0] ram_wdata ;
wire ram_write ;
ram_ahbif U_ram_ahbif(
.hclk (hclk ),
.hresetn (hresetn ),
.hsel_s (hsel_s ),
.haddr_s (haddr_s ),
.hburst_s (hburst_s ),
.htrans_s (htrans_s ),
.hrdata_s (hrdata_s ),
.hwdata_s (hwdata_s ),
.hwrite_s (hwrite_s ),
.hready_s (hready_s ),
.hresp_s (hresp_s ),
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