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High Performance Single Ended to Differential Active
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TI High Speed Designs: Verified Design High Performance Single Ended to Differential Active Interface for High Speed ADCs
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An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and
other important disclaimers and information.
TINA-TI is a trademark of Texas Instruments
WEBENCH is a registered trademark of Texas Instruments
TIDA-00294-August 2014 High Performance Single Ended to Differential Active Interface for High Speed ADCs
1
Copyright © 2014, Texas Instruments Incorporated
Ken Chan, Michael Steffes
TI High Speed Designs: Verified Design
High Performance Single Ended to Differential Active
Interface for High Speed ADCs
TI High Speed Designs Circuit Description
TI High Speed Designs are analog solutions created
by TI’s analog experts. Verified Designs offer the
theory, component selection, simulation, complete
PCB schematic & layout, bill of materials, and
measured performance of useful circuits. Circuit
modifications that help to meet alternate design goals
are also discussed.
The quad channel DEV-ADC34J22 board from Dallas
Logic offers an example of a DC coupled single to
differential channel using the THS4541 wideband
Fully Differential Amplifier driving an ADC34J22. This
type of circuit may be used in sensor front end, motor
control, and test equipment applications. The
amplifier circuit implemented on this EVM has a
voltage gain of 2x. Applying a maximum 1Vpp ground
centered input to one of the inputs, will result in a
2Vpp differential signal centered at 0.95V common
mode at the ADC input pins. Included in this path is a
low insertion loss 20MHz Bessel filter to limit the SNR
degradation.
Design Resources
ADC34J22EVM Product Folder
DEV-ADC34J22 EVM Product Folder
ADC3XJXX Design EVM Design Package
Ask The Analog Experts
WEBENCH® Design Center
TI Precision Designs Library
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www.ti.com
2 High Performance Single Ended to Differential Active Interface for High Speed ADCs TIDA-00294-August 2014
Copyright © 2014, Texas Instruments Incorporated
1 ADC34J22 and THS4541 Configuration
The DEV-ADC34J22 EVM from Dallas Logic has 4 channels: Channels 1 and 2 are transformer/AC coupled
single-to-differential paths, while channels 3 and 4 are active DC coupled single-to-differential paths utilizing a
THS4541 fully differential amplier. All 4 paths expect a 50 ohm source. For AC coupled passive performance the
transformer paths should be used. In this document we will focus on the ADC34J22 + THS4541 implementation
for simplicity sake – however the circuit applications are very similar for the entire ADC3XXXX family.
ADC Device
Interface
#channels
# bits
Max Msps
ADC3221
ADC3222
ADC3223
ADC3224
ADC3241
ADC3242
ADC3243
ADC3244
sLVDS
Dual
12
12
12
12
14
14
14
14
25
50
80
125
25
50
80
125
ADC3421
ADC3422
ADC3423
ADC3424
ADC3441
ADC3442
ADC3443
ADC3444
sLVDS
Quad
12
12
12
12
14
14
14
14
25
50
80
125
25
50
80
125
ADC32J22
ADC32J23
ADC32J24
ADC32J25
ADC32J42
ADC32J43
ADC32J44
ADC32J45
JESD204B
Dual
12
12
12
12
14
14
14
14
50
80
125
160
50
80
125
160
ADC34J22
ADC34J23
ADC34J24
ADC34J25
ADC34J42
ADC34J43
ADC34J44
ADC34J45
JESD204B
Quad
12
12
12
12
14
14
14
14
50
80
125
160
50
80
125
160
Table 1. List of available ADC3xxxx devices.
The block diagram of the DEV-ADC34J22 EVM is shown in figure 1. It is comprised of the ADC34J22, the
THS4541 devices for the amplifier path, and the LMK04828B for clocking. The connection to the FPGA is
through an HSMC connector. Configuration of the LMK04828B and the ADC34J22 is through the SPI interface
through the HSMC connector from the FPGA. Refer to the Dallas Logic EVM link for details on ADC and LMK
configuration.
Power for the ADC is provided from a TPS7A8101 LDO which regulates the 3.3V from the HSMC connector to
1.8V for the ADC.
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