module dpll(reset,clk,signal_in,signal_out,syn);
parameter para_K=4;
parameter para_N=16;
input reset;
input clk;
input signal_in;
output signal_out;
output syn;
reg signal_out;
reg dpout;
reg delclk;
reg addclk;
reg add_del_clkout;
reg [7:0] up_down_cnt;
reg [2:0] cnt8;
reg [8:0] cnt_N;
reg syn;
reg dpout_delay;
reg [8:0] cnt_dpout_high;
reg [8:0] cnt_dpout_low;
/*****phase detector******/
always @ (signal_in or signal_out)
begin
dpout<=signal_in^signal_out;
end
/******synchronization establish detector******/
always @ (posedge clk or negedge reset)
begin
if(!reset) dpout_delay<='b0;
else dpout_delay<=dpout;
end
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
cnt_dpout_high<='b0; cnt_dpout_low<='b0;
end
else if(dpout)