基于Verilog的数字锁相环设计,在vivado2019.2中开发带testbench+代码操作视频
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2022-05-29
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基于Verilog的数字锁相环设计,在vivado2019.2中开发带testbench.rar （62个子文件） 
4基于Verilog的数字锁相环设计,在vivado2019.2中开发带testbench 
操作录像0021.avi 11.12MB project_13 project_13.ip_user_files 
README.txt 130B project_13.cache wt 
webtalk_pa.xml 3KB project.wpc 61B gui_handlers.wdf 2KB java_command_handlers.wdf 608B xsim.wdf 256B compile_simlib questa xcelium ies modelsim vcs riviera activehdl project_13.sim sim_1 behav xsim xsim.dir xil_defaultlib pi_filter.sdb 2KB @debounce_@clock_@div.sdb 1KB pll_top.sdb 1KB spll.sdb 5KB phase_detector.sdb 2KB integral_adder.sdb 2KB spll_tb.sdb 2KB debouncer.sdb 1KB xil_defaultlib.rlx 1KB top_tb.sdb 1KB @flip_@flop.sdb 588B glbl.sdb 4KB spll_tb_behav xsimcrash.log 0B TempBreakPointFile.txt 29B xsim.dbg 9KB xsim.xdbg 3KB obj xsim_1.win64.obj 4KB xsim_0.win64.obj 19KB xsim_1.c 6KB
xsimk.exe 78KB xsimkernel.log 221B xsim.type 24B xsim.mem 4KB xsim.rtti 190B xsimSettings.ini 1KB webtalk 
usage_statistics_ext_xsim.html 3KB usage_statistics_ext_xsim.xml 3KB .xsim_webtallk.info 64B Compile_Options.txt 248B xsim.svtype 39B xsim.reloc 2KB xsim.rlx 797B xvlog.log 0B webtalk_2171428.backup.jou 883B spll_tb_vlog.prj 237B xvlog.pb 16B webtalk.jou 883B simulate.bat 908B compile.log 0B spll_tb_behav.wdb 34.24MB xsim.ini 40B spll_tb.tcl 460B elaborate.bat 1KB glbl.v 1KB elaborate.log 749B top_tb_vlog.prj 459B simulate.log 0B xelab.pb 1KB webtalk_2171428.backup.log 1KB .Xil Webtalk-2171428-DESKTOP-VH31686 webtalk Webtalk-2178592-DESKTOP-VH31686 webtalk webtalk.log 1KB compile.bat 834B project_13.hw project_13.lpr 290B ace spll.v 4KB spll_tb.v 847B project_13.xpr 9KB
fpga和matlab
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