matlab-(含教程)基于FPGA的SDR维特比译码器设计,码率等于0.5,约束长度等于9,回溯深度等于5

# Verilog #Viterbi Decoder Design For SDR on an FPGA Code Rate = ½, Constraint Length (K) = 9 Some consequences of using a constraint length of 9 are: The amount of branch metric is 2 K = 512 branches. The amount of state metric is 2 K-1 = 256 states. The depth of trace back process is at least = 5 Params.v is a not a simulation file ,for the code to run copy this file to your project folder