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performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
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sion of device specifications before relying on any published information and before placing orders for
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Contents
Chapter Revision Dates .......................................................................... vii
About this Handbook ................................................................................ i
How to Contact Altera ............................................................................................................................... i
Typographic Conventions ......................................................................................................................... i
Section I. Stratix II Device Family Data Sheet
Revision History ....................................................................................................................... Section I–2
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–1
Chapter 2. Stratix II Architecture
Functional Description .......................................................................................................................... 2–1
Logic Array Blocks ................................................................................................................................ 2–3
LAB Interconnects ............................................................................................................................ 2–4
LAB Control Signals ......................................................................................................................... 2–5
Adaptive Logic Modules ...................................................................................................................... 2–6
ALM Operating Modes ................................................................................................................... 2–9
Register Chain ................................................................................................................................. 2–20
Clear & Preset Logic Control ........................................................................................................ 2–22
MultiTrack Interconnect ..................................................................................................................... 2–22
TriMatrix Memory ............................................................................................................................... 2–28
Memory Block Size ......................................................................................................................... 2–29
Digital Signal Processing Block ......................................................................................................... 2–40
Modes of Operation ....................................................................................................................... 2–44
DSP Block Interface ........................................................................................................................ 2–44
PLLs & Clock Networks ..................................................................................................................... 2–48
Global & Hierarchical Clocking ................................................................................................... 2–48
Enhanced & Fast PLLs ................................................................................................................... 2–57
Enhanced PLLs ............................................................................................................................... 2–69
Fast PLLs .......................................................................................................................................... 2–70
I/O Structure ........................................................................................................................................ 2–71
Double Data Rate I/O Pins ........................................................................................................... 2–79
External RAM Interfacing ............................................................................................................. 2–83
Programmable Drive Strength .....................................................................................................2–85
Open-Drain Output ........................................................................................................................ 2–86
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Contents Stratix II Device Handbook, Volume 1
Bus Hold .......................................................................................................................................... 2–86
Programmable Pull-Up Resistor .................................................................................................. 2–87
Advanced I/O Standard Support ................................................................................................ 2–87
On-Chip Termination .................................................................................................................... 2–91
MultiVolt I/O Interface ................................................................................................................. 2–95
High-Speed Differential I/O with DPA Support ............................................................................ 2–98
Dedicated Circuitry with DPA Support .................................................................................... 2–102
Fast PLL & Channel Layout ........................................................................................................ 2–104
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support ............................................................................... 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–4
Configuration ......................................................................................................................................... 3–4
Operating Modes .............................................................................................................................. 3–5
Configuration Schemes ................................................................................................................... 3–7
Configuring Stratix II FPGAs with JRunner ............................................................................... 3–10
Programming Serial Configuration Devices with SRunner ..................................................... 3–10
Configuring Stratix II FPGAs with the MicroBlaster Driver ................................................... 3–11
PLL Reconfiguration ...................................................................................................................... 3–11
Temperature Sensing Diode ............................................................................................................... 3–11
Automated Single Event Upset (SEU) Detection ............................................................................ 3–13
Custom-Built Circuitry .................................................................................................................. 3–14
Software Interface ........................................................................................................................... 3–14
Chapter 4. Hot Socketing & Power-On Reset
Stratix II
Hot-Socketing Specifications ............................................................................................................... 4–1
Devices Can Be Driven Before Power-Up .................................................................................... 4–2
I/O Pins Remain Tri-Stated During Power-Up ........................................................................... 4–2
Signal Pins Do Not Drive the V
CCIO
, V
CCINT
or V
CCPD
Power Supplies .................................... 4–2
Hot Socketing Feature Implementation in Stratix II Devices .......................................................... 4–3
Power-On Reset Circuitry .................................................................................................................... 4–5
Chapter 5. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 5–1
Absolute Maximum Ratings ........................................................................................................... 5–1
Recommended Operating Conditions .......................................................................................... 5–2
DC Electrical Characteristics .......................................................................................................... 5–3
I/O Standard Specifications ........................................................................................................... 5–4
Bus Hold Specifications ................................................................................................................. 5–17
On-Chip Termination Specifications ........................................................................................... 5–17
Pin Capacitance .............................................................................................................................. 5–19
Power Consumption ........................................................................................................................... 5–20
Timing Model ....................................................................................................................................... 5–20
Preliminary & Final Timing .......................................................................................................... 5–20
I/O Timing Measurement Methodology .................................................................................... 5–21
Performance .................................................................................................................................... 5–27
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Contents Contents
Internal Timing Parameters .......................................................................................................... 5–34
Stratix II Clock Timing Parameters .............................................................................................. 5–41
Clock Network Skew Adders .......................................................................................................5–50
IOE Programmable Delay ............................................................................................................. 5–51
Default Capacitive Loading of Different I/O Standards .......................................................... 5–52
I/O Delays ....................................................................................................................................... 5–54
Maximum Input & Output Clock Toggle Rate .......................................................................... 5–66
Duty Cycle Distortion ......................................................................................................................... 5–77
DCD Measurement Techniques ................................................................................................... 5–78
High-Speed I/O Specifications .......................................................................................................... 5–87
PLL Timing Specifications .................................................................................................................. 5–91
External Memory Interface Specifications ....................................................................................... 5–94
JTAG Timing Specifications ............................................................................................................... 5–96
Chapter 6. Reference & Ordering Information
Software .................................................................................................................................................. 6–1
Device Pin-Outs ..................................................................................................................................... 6–1
Ordering Information ........................................................................................................................... 6–1
