Stratix_II_GX_Ver1_01_user.zip_STRATIX _Stratix? II GX_stratix i

Altera Stratix II GX Design Kit http://www.altera.com/technology/signal/devices/stratix2gx/sgl-s2gx.html Draft Release 20th December 2007: ================================= 1. Only TX & RX components with symbols, bitmaps and formsets. 2. No netlist/simulation capability. Demo Version 16th January 2008: =============================== For initial user demo. Version 1.0 25th January 2008: =============================== To install this Design Kit please follow the procedure outlined in the Design Kit Installation and Setup manual, Chapter 2, ($HPEESOF_DIR/doc/pdf/dkug.pdf). 1. The Design Kit contains 6 basic components to reproduce the same style of simulations as configured in the HSPICE netlists provided. These are a Controller, TX, RX, Rext, Clock and Signal Generator. 2. The HSPICE netlist files used as models and setting configuration do not support the possibility of ADS using hierarchical structures in schematic. All Design Kit elements must exist on the same schematic. A Controller element is required on all designs but only one can be place in any design. 3. Multiple TX, RX, Clock Sources and Signal Generators are allowed in a single design but all TXs and all RXs must use the same configuration settings. 4. Each external load resistors element are associated with only one TX and must have the appropriate TX_ID set to configure the correct matching resistance. Regular ADS resistors could be used also but them the user would need to manually define the required resistant value. 5. The default setting for each Clock Source and Signal Generator is to use the values of tdrate and trfx as set in the Controller component. However, these values can be change on each Clock and Signal Generator separately as required. 6. For the Signal Generator and each source for the TX elements DE/DO inputs (these are built into the TX element itself) the user can set the required PRBS parameters. The Taps and Seed parameters can be set to have different data applied to each input as required. The shortest length value of either Taps or Seed sets the number of registers in that source. The data can also be delayed or have random jitter applied by setting each Delay and RJrms parameter. 7. Measurement probes are internally configured in each of the elements to be able to observe time-domain waveforms at each device port, both single-ended and differential measurements, but node names need to be added to these nodes to be viewed. 8. Four schematic templates are available for typical starting cases are available within the Design Kit. These are for: Single RX with Signal Generator - Stratix_II_GX_RX_Template Single TX with load resistor - Stratix_II_GX_TX_Template TX and RX with DC coupled connection - Stratix_II_GX_TX_RX_DC_Coupled_Template TX and RX with AC coupled connection - Stratix_II_GX_TX_RX_AC_Coupled_Template To select the required template in the schematic window select Files > New... and in the next window enter the desired new file name and then in the Design Content section use the drop-down list to select the required template. The Design Kit templates will typically be listed at the bottom of the list. For the AC coupled template the Initial Conditions setting for both the TX and RX components has been set to On. The default setting is Off. 9. There are two models defined for RX components by this process. One is used when only RX components are used, rx.cir, the other is used when any TX component also exists on the same schematic, rx_run_w_tx_only.cir. The netlisting functions provided by this Design Kit detect if a TX element is present and netlists the correct model file automatically. The user does not need to make any changes to the design for this to happen. Version 1.01 7th July 2008: ============================ Minor adjustment to configuration files to better support operation on UNIX/Linux platforms.