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UB981寄存器手册,比较老的版本
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UB981寄存器手册,比较老的版本
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TI Confidential – NDA Restrictions
DS90UB981-Q1 4K DSI to FPD-Link IV Bridge Serializer
1 Features
• Single or dual port MIPI DSI receiver
– Compliant to D-PHY v1.2 and DSI v1.3.1
– Packed 16/18/24/30-bit RGB and 16-bit YCbCr
– Loosely packed 18-bit RGB and 20-bit 4:2:2
– 1 clock lane and 1-4 configurable data lanes
per D-PHY Port
– Up to 2.5 Gbps/lane with skew calibration
– Supports data lane swap and polarity inversion
– Supports both burst and non-burst mode
– SuperFrame Unpacking Capability
– Suitable for 4K @ 60 Hz video resolution
• FPD-link IV interface
– Supports 10.8/6.75/3.375 Gbps per channel;
Up to 21.6 Gbps over dual channels
– Coax/STP interconnect support
– Port Splitting to enable Y-cable interfaces
• Ultra-low latency control channel
– Two I2C up to 1MHz (up to 3.4 MHz for local
bus access)
– High speed GPIOs
• Backwards compatible
– 720P 92x and 1080P/2K 94x product families
– ADAS 936, 954, 960, 962, 9702 , 9722
deserializers
• Security and diagnostics
– Voltage and temperature monitoring
– Line Fault Detection
– BIST and pattern generation
– CRC and error diagnostics
– Unique ID for counterfeit protection
– ECC on control bits
• Advanced link robustness and EMC control
– Data scrambling
– Spread spectrum clocking generation (SSCG)
• Low power operation
– 1.8-V and 1.15-V dual power supply
• AEC-Q100 qualified for automotive applications
– AEC-Q100 grade-level 2: −40℃ to +105℃
– 64 pin QFN Wettable flanks 9 mm x 9 mm
– ISO 10605 and IEC 61000-4-2 ESD compliant
2 Applications
• Automotive displays:
– Central Information Displays (CID)
– Rear Seat Entertainment (RSE)
– Digital instrument clusters
– Head units and HMI modules
– Head Up Display (HUD)
– Rear view and side mirror displays
3 Description
DS90UB981-Q1 is a MIPI DSI to FPD-Link III/IV
bridge device. In conjunction with an FPD-Link IV
deserializer, the chipset provides a high-speed
serialized interface over low-cost 50Ω coax or STP
cables. The DS90UB981-Q1 is a D-PHY v1.2
compliant device that serializes a MIPI DSI input
supporting video resolutions including 4K with 30-bit
color depth. The FPD-Link IV interface supports video
and audio data transmission and full duplex control,
including I2C and GPIO data over a single channel or
dual channels. Consolidation of video data and control
over two FPD-Link IV lanes reduces the interconnect
size and weight and simplifies system design. EMI is
minimized by the use of low voltage differential
signaling, data scrambling, SSCG, and randomization.
In backward compatible mode, the devices supports
up to 720p and 1080p resolutions with 24-bit color
depth over a single/dual link. In ADAS compatible
mode, the device is interoperable with 936, 95x, 96x &
97x deserializer supporting resolutions up to 8MP+/
40fps.
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UB981-Q1 VQFN RTD (64) 9.00 mm × 9.00 mm
Secondary
Display
DS90Ux988
Deserializer
DS90Ux981
Serializer
FPD-Link IV
(over Coax or STP)
DOUT0+
DOUT0-
DOUT1+
DOUT1-
RIN0+
RIN0-
RIN1+
RIN1-
Open LDI
Display
or Graphics
Processor
Processor
DOUT+
DOUT-
IDx
I2C
MIPI DSI
IDx
I2C
D0+/-
D1+/-
D2+/-
D3+/-
CHn_TX0P/N
CHn_TX1P/N
CHn_TX2P/N
CHn_CLKP/N
CLK+/-
D0+/-
D1+/-
D2+/-
D3+/-
CLK+/-
CHn_TX3P/N
CHn_TX4P/N
Simplifed Application Diagram
www.ti.com
DS90UB981-Q1
SLUSE46 – SEPTEMBER 2020
PRODUCT PREVIEW
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
1
DS90UB981-Q1
SLUSE46 – SEPTEMBER 2020
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of
development. Subject to change or discontinuance without notice.
TI Confidential – NDA Restrictions
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
6 Specifications.................................................................. 9
6.1 Absolute Maximum Ratings ....................................... 9
6.2 ESD Ratings .............................................................. 9
6.3 Thermal Information .................................................10
6.4 Recommended Operating Conditions ......................10
6.5 DC Electrical Characteristics ................................... 10
6.6 AC Electrical Characteristics ....................................15
6.7 AC Electrical Characteristics DSI .............................17
6.8 Recommended Timing for the Serial Control Bus ....22
6.9 Timing Diagrams....................................................... 24
7 Detailed Description......................................................26
7.1 Overview................................................................... 26
7.2 Functional Block Diagram......................................... 28
7.3 Feature Description...................................................28
7.4 Device Functional Modes..........................................65
7.5 Programming............................................................ 67
7.6 Register Map.............................................................72
8 Application and Implementation................................ 338
8.1 Typical Application.................................................. 338
9 Power Supply Recommendations..............................344
9.1 Power Up Requirements And PDB Pin...................344
10 Layout.........................................................................345
10.1 Layout Guidelines................................................. 345
11 Device and Documentation Support........................360
11.1 Documentation Support........................................ 360
11.2 Trademarks........................................................... 360
11.3 Electrostatic Discharge Caution............................ 360
11.4 Glossary................................................................ 360
12 Mechanical, Packaging and Orderable
Information.................................................................. 360
4 Revision History
DATE REVISION NOTES
February 2018 * Initial Release
May 2018 0.1
-Updated Features, Added Power
Consumption table
June 2018 0.2 -Updated Pin 40 description, FPD4 linerate
March 2019 0.3
-Updated Pin 40 description, Updated
Features, Update Reference Clock
Recommendation
July 2019 0.4
-Updated Max Current and Power
Consumption, Updated POD
Aug 2019 0.5 -Added register map and features description
April 2020 0.6
• Added ADAS compatibility, Line fault
detection, voltage sensing and
temperature monitoring
• Updated SSCG equations
DS90UB981-Q1
SLUSE46 – SEPTEMBER 2020
www.ti.com
PRODUCT PREVIEW
2 Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
TI Confidential – NDA Restrictions
DATE REVISION NOTES
Sept 2020 1.0
• VDD11 changed from 1.1V to 1.15V
• Updated Abs Max of VDD11, DSI input
voltage, FPD-Link IV output voltage,
Reserved pin voltage from 1.21V to
1.32V
• Increased max current consumption on
the VDD18 supply from 150 mA to 250
mA
• Decreased max current consumption on
the VDD11 supply from 1000 mA to 815
mA
• Increased Total Power Consumption to
1.46 W from 1.45 W
• Removed 13.5 Gbps support
• Changed pin 13 to MODE_SEL2
• Updated MODE_SEL section with ADAS
and IVI MODE_SEL0,1,2 values
• Updated MODE_SEL section
recommended resistor values
• Renamed pins 12 to RES2
• Added coxial typical connection diagram
• Updated packaging diagrams
• Added Layout Guidelines Section
• Added exposed pad recommendation for
thermal relief section
• Updated Power Up Requirements And
PDB Pin Section
• Added ADC register page
• Added new registers sets
• Updated t(BUF) for FPD3 to 2µs when
PCLK = 25MHz in FPD3 mode
• Updated Output Total Jitter TYP value to
0.35 UI
• Updated Device block diagram
• Removed Center-Spread spectrum
• Removed PLL Peaking specification from
Electrical Characteristics table
www.ti.com
DS90UB981-Q1
SLUSE46 – SEPTEMBER 2020
PRODUCT PREVIEW
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
3
TI Confidential – NDA Restrictions
5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DS90Ux981-Q1
64L QFN
Top down view
DAP = GND
DSI0_D3N
DSI1_D1N
DSI1_D1P
DSI1_D2P
DSI0_D1N
DSI0_D0N
DSI0_D1P
DSI0_D0P
DSI0_CLKN
DSI0_CLKP
GPIO1
GPIO9
DOUT1+
I2C_SDA0
INTB
PDB
VDD11_L
DSI1_CLKP
DOUT0+
VDD11_HS0
VDDIO
DOUT0-
VDD11_HS1
DOUT1-
DSI1_D3N
VDD18
DSI1_D2N
DSI1_D3P
VDD11_DSI
DSI0_D3P
GPIO5/I2S_DB
GPIO2/I2S_DC
DSI0_D2P
RBIAS
MODE_SEL0
IDX
GPIO13/SS
RES0
VDD11_P1
REFCLK0
GPIO3/I2S_DD
RES1
DSI1_D0P
DSI1_CLKN
VDD11_S
VDD18
GPIO12/SPLK/I2C_SCL1
I2C_SCL0
GPIO11/MISO/I2C_SDA1
GPIO10/MOSI
GPIO0
MODE_SEL2
REFCLK1
VDDIO
GPIO6/I2S_DA
GPIO7/I2S_WC
GPIO8/I2S_CLK
GPIO4/REM_INTB
MODE_SEL1
DSI0_D2N
VDD11_L
DSI1_D0N
VDD11_P0
RES2
Figure 5-1. RTD Package 64-Pin VQFN Top View
Pin Functions
PIN
I/O, TYPE DESCRIPTION
NAME NO.
MIPI DSI INPUT PINS
DSI0_D0P 58 I DSI Channel 0 Input Data Lane 0
If unused, tie to Ground.
DSI0_D0N 57 I
DSI0_D1P 56 I DSI Channel 0 Input Data Lane 1
If unused, tie to Ground.
DSI0_D1N 55 I
DSI0_D2P 54 I DSI Channel 0 Input Data Lane 2
If unused, tie to Ground.
DSI0_D2N 53 I
DSI0_D3P 52 I DSI Channel 0 Input Data Lane 3
If unused, tie to Ground.
DSI0_D3N 51 I
DSI0_CLKP 60 I DSI Channel 0 Input Clock Lane
If unused, tie to Ground.
DSI0_CLKN 59 I
DSI1_D0P 6 I DSI Channel 1 Input Data Lane 0
If unused, tie to Ground.
DSI1_D0N 5 I
DSI1_D1P 4 I DSI Channel 1 Input Data Lane 1
If unused, tie to Ground.
DS90UB981-Q1
SLUSE46 – SEPTEMBER 2020
www.ti.com
PRODUCT PREVIEW
4 Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
TI Confidential – NDA Restrictions
PIN
I/O, TYPE DESCRIPTION
NAME NO.
DSI1_D1N 3 I
DSI1_D2P 2 I DSI Channel 1 Input Data Lane 2
If unused, tie to Ground.
DSI1_D2N 1 I
DSI1_D3P 63 I DSI Channel 1 Input Data Lane 3
If unused, tie to Ground.
DSI1_D3N 62 I
DSI1_CLKP 8 I DSI Channel 1 Input Clock Lane
If unused, tie to Ground.
DSI1_CLKN 7 I
FPD-LINK IV INTERFACE PINS
DOUT0– 26 I/O FPD-Link IV Inverting Input/Output 0
The pin must be AC-coupled with a 100nF capacitor. It is recommended these PCB
traces maintain 100 Ω differential impedance. It can interface with a compatible FPD-Link
III/IV deserializer RX through an STP or coaxial cable. In Coax configuration the AC-
Coupling capacitor for DOUT+ should be 100nf and DOUT- should be 47 nf. If port
unused, leave pin as No Connect.
DOUT0+ 27
DOUT1– 22 I/O FPD-Link IV Inverting Input/Output 1
The pin must be AC-coupled with a 100nF capacitor. It is recommended these PCB
traces maintain 100 Ω differential impedance. It can interface with a compatible FPD-Link
III/IV deserializer RX through an STP or coaxial cable. In Coax configuration the AC-
Coupling capacitor for DOUT+ should be 100nf and DOUT- should be 47 nf. If port
unused, leave pin as No Connect.
DOUT1+ 23
CLOCK REFERENCE PINS
REFCLK0 41 I External Oscillator Input
This pin is the primary clock reference input. It must be connected to an external CMOS-
level 1.8V 27 MHz oscillator source (+/-100ppm).
REFCLK1 11 I Reference Clock Input For Backward Compatibility
This clock is used only when connecting to FPD-Link III devices requiring a specific
PCLK frequency; however REFCLK0 may still be used for backwards compatibility. The
clock frequency is 16.5MHz - 33MHz (+/-100 ppm). This is optional; If unused leave as
No Connect.
CONTROL PINS
I2C_SDA0 48 I/O, OD I2C Data Input / Output Interface
Open drain. Typically pulled up by 2.2kΩ resistors to 1.8V or 4.7kΩ resistors to 3.3V.
If unused leave as No Connect.
I2C_SCL0 47 I/O, OD I2C Clock Input / Output Interface
Open drain. Typically pulled up by 2.2kΩ resistors to 1.8V or 4.7kΩ resistors to 3.3V. If
unused leave as No Connect.
GPIO11/MISO/
I2C_SDA1
45 I/O, PD General Purpose Input/Output 11
Shared with MISO and I2C_SDA1
When used as I2C_SDA1, typically pulled up by 2.2kΩ resistors to 1.8V
Pin functionality defaults to I2C with an internal 25 kΩ pull down resistor disabled.
If unused leave as No Connect.
GPIO12/SPLK/
I2C_SCL1
44 I/O, PD General Purpose Input/Output 12
Shared with SPLK and I2C_SCL2
When used as I2C_SCL2, typically pulled up by 2.2kΩ resistors to 1.8V
Pin functionality defaults to I2C with an internal 25 kΩ pull down resistor disabled.
If unused leave as No Connect.
IDX 19 I, S I2C Address Select
See Table 7-33 for
Pull-up to VDD18 (pin 24) is required under all conditions. DO NOT LEAVE OPEN OR
NO CONNECT.
Connect to external pull-up and pull-down resistors to create a voltage divider.
MODE_SEL0 18 I, S Mode Select 0 Input. See Table 7-29
MODE_SEL1 32 I, S Mode Select 1 Input. See Table 7-30
www.ti.com
DS90UB981-Q1
SLUSE46 – SEPTEMBER 2020
PRODUCT PREVIEW
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
5
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