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远古版本的983寄存器手册,可能和最新的硬件有些出入,但是大体是一样的。 优点是有些已经不开放的寄存器描述这里可以找到,但是不保证适用最新的硬件
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TI Confidential – NDA Restrictions
PRODUCTPREVIEW
TI Confidential — NDA Restrictions
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of
development. Subject to change or discontinuance without notice.
DS90UB983-Q1
SNLS606 –MARCH 2020
DS90UB983-Q1 4K DisplayPort to FPD-Link IV Bridge Serializer
1
1 Features
1
• DisplayPort Receiver
– DP v1.4 Compliant
– HBR3/HBR2/HBR/RBR Link Bit Rates
– Main Link: 1, 2, or 4 Lanes
– Each Lane up to 8.1 Gbps
– AUX CH 1 Mbps
– Hot Plug Detect (HPD)
– Multi-Display (MST) and SST support
– Daisy Chaining & Splitting
– SuperFrame Unpacking Capability
– Suitable for 4K @ 60 Hz Video Resolution
• FPD-Link IV Interface
– Supports 13.5/10.8/6.75/3.375 Gbps per
channel; Up to 27 Gbps over dual channels
– Coax/STP Interconnect Support
– Port Splitting to Enable Y-cable Interfaces
– MST and SuperFrame Based Data Splitting to
Different FPD Channels
• Ultra-low Latency Control Channel
– Three Fast-Mode Plus I2C up to 1 MHz (up to
3.4 MHz for local bus access)
– High Speed GPIOs
• Backwards Compatibility
– IVI 94x and 92x Product Families
• Security and Diagnostics
– Link Diagnostics
– Voltage and Temperature Monitoring
– BIST and Pattern Generation
– CRC and Error Diagnostics
– ECC Error Correction for Control Bits
– Replica Mode for Redundancy
• Advanced Link Robustness and EMC Control
– Spread Spectrum Clocking (SSC) Input
Support
– Spread Spectrum Clocking Generation (SSCG)
– Data Scrambling
• Low Power Operation
– 1.8V and 1.1V Dual Power Supply
– <1.9W Typ Power Dissipation
• AEC-Q100 Qualified for Automotive Applications
– AEC-Q Grade-Level 2, -40°C to 105°C
– 64-pin QFN Wettable flanks 9 mm x 9 mm
– ISO 10605 and IEC 61000-4-2 ESD Compliant
2 Applications
• Automotive Displays:
– Central Information Display (CID)
– Rear Seat Entertainment (RSE)
– Digital Instrument Clusters
– Head Units and HMI Modules
– Head Up Display (HUD)
– Rear View & Side Mirror Displays
3 Description
The DS90UB983-Q1 is a DisplayPort to FPD-Link IV
bridge device. In conjunction with an FPD-Link IV
deserializer, the chipset provides a high-speed
serialized interface over low-cost 50Ω coax or STP
cables. The DS90UB983-Q1 is a VESA DP Standard
v1.4 compliant device that supports advanced
features such as MST, HBR3, and SuperFrame
formats. The device is capable of supporting video
resolution up to 4K resolutions with 30-bit color.
8b10b encoded DP data is serialized onto an FPD-
Link IV interface output. The FPD-Link IV interface
supports video and audio data transmission and full
duplex control, including I2C, and GPIO data over a
single channel or dual channels. Consolidation of
video data and control over FPD-Link IV lanes
reduces the interconnect size and weight and
simplifies system design. EMI is minimized by the use
of low voltage differential signaling, data scrambling,
and randomization. In backward compatible mode,
the device supports up to 720p and 1080p resolutions
with 24-bit color depth over a single/dual link.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UB983-Q1 QFN (64) 9.0 mm × 9.0 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
TI Confidential – NDA Restrictions
PRODUCTPREVIEW
DS90Ux984-Q1
Deserializer
DS90Ux983-Q1
Serializer
FPD-Link IV
(over Coax or STP)
DOUT0+
DOUT0-
DOUT1+
DOUT1-
RIN0+
RIN0-
RIN1+
RIN1-
eDP
Graphics
Processor
DisplayPort
AUX
CH
D0±
D1±
D2±
D3±
IDx
HS_GPIO
I2C
IDx
I2C
Secondary
Display
DOUT0+
DOUT0-
DOUT1+
DOUT1-
TX Port0:
Up to 4 Lanes plus
AUX and HPD
TX Port1:
Up to 4 Lanes plus
AUX and HPD
Display
or Graphics
Processor
Display
or Graphics
Processor
HPD
HS_GPIO
TI Confidential — NDA Restrictions
2
DS90UB983-Q1
SNLS606 –MARCH 2020
www.ti.com
Product Folder Links: DS90UB983-Q1
Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated
4 Simplified Application Diagram
TI Confidential – NDA Restrictions
PRODUCTPREVIEW
TI Confidential — NDA Restrictions
3
DS90UB983-Q1
www.ti.com
SNLS606 –MARCH 2020
Product Folder Links: DS90UB983-Q1
Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Application Diagram............................ 2
5 Revision History..................................................... 3
6 Pin Configuration and Functions......................... 5
7 Specifications......................................................... 9
7.1 Absolute Maximum Ratings ...................................... 9
7.2 ESD Ratings.............................................................. 9
7.3 Thermal Information.................................................. 9
7.4 Recommended Operating Conditions..................... 10
7.5 DC Electrical Characteristics .................................. 10
7.6 AC Electrical Characteristics................................... 17
7.7 DisplayPort Electrical Characteristics ..................... 20
7.8 Recommended Timing for the Serial Control Bus .. 23
7.9 Timing Diagrams..................................................... 24
8 Detailed Description............................................ 26
8.1 Overview ................................................................. 26
8.2 Functional Block Diagram ....................................... 27
8.3 Feature Description................................................. 27
8.4 Device Functional Modes........................................ 51
8.5 Programming........................................................... 53
8.6 Register Map........................................................... 59
9 Application and Implementation ...................... 255
9.1 Power Consumption.............................................. 255
9.2 Typical Applications .............................................. 255
10 Layout................................................................. 258
10.1 Layout Guidelines ............................................... 258
11 Device and Documentation Support ............... 260
11.1 Documentation Support ..................................... 260
11.2 Trademarks ......................................................... 260
11.3 Electrostatic Discharge Caution.......................... 260
11.4 Glossary .............................................................. 260
12 Mechanical, Packaging, and Orderable
Information ......................................................... 261
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
February 2018 * Initial release.
May 2018 0.1
-Updated Features, Description, Application
Diagram, Pin Configuration and Functions,
Overview, Functional Block Diagram
June 2018 0.2
-Updated FPD4 linerate, Application diagram,
Orderable device p/n
July 2018 0.3
-Updated Pin Descriptions
-Updated Pinout
Pin 74: Reassigned to VDD11_DP0_0
Pin 29: Reassigned to VDD18_FPD
Pin 20: Added I2S_WC shared with GPIO[7]
Pin 51: Added I2S_CLK shared with GPIO[8]
Pin 19: Added I2S_DA shared with GPIO[6]
Pin 18: Added I2S_DB shared with GPIO[5]
Pin 15: Added I2S_DC shared with GPIO[2]
Pin 16: Added I2S_DD shared with GPIO[3]
-Added Typical Application Connection Diagram
-Updated Power Consumption values
August 2018 0.4
-Updated Pinout and Package (64L)
-Updated Pin Descriptions
November 2018 0.5
-Updated main body of document to reflect initial
sample features and operation
December 3 2018 0.6 -Updated packaging diagrams
December 4 2018 0.7
-Updated recommended strap resistors to be
<100kOhm
March 25 2019 0.8
-Renamed REFCLK2 pin to REFCLk1, renamed
I2C_SCL/SDA to I2C_SCL0/SDA0,
I2C_SCL2/SDA2 to I2C_SCL1/SDA1,
I2C_SCL3/SDA3 to I2C_SCL2/SDA2, renamed
VDD18_AON to RES2, renamed SIG_DETECT to
RES3
- Updated datasheet to match ES2.0
May 16 2019 0.9
-Updated block diagram, updated register
formatting, added minimum PCLK to video
processor frequency section
TI Confidential – NDA Restrictions
PRODUCTPREVIEW
TI Confidential — NDA Restrictions
4
DS90UB983-Q1
SNLS606 –MARCH 2020
www.ti.com
Product Folder Links: DS90UB983-Q1
Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated
Revision History (continued)
DATE REVISION NOTES
December 2, 2019 1.0
- Updated pinout configuration
- Updated pinout description
- Updated typical connection diagram from
Applications section
- Pulled in the new specification
-Removed power table in applications section
March 16, 2020 1.1 -Added 10.8 and 3.375 Gbps in AC table
TI Confidential – NDA Restrictions
PRODUCTPREVIEW
48 VDD11_DP_PLL1DP_TESTP
49RES0 32 MODE_SEL1
47 INTB2DP_TESTN
50RES1 31 PDB
46 VDD11_L3VDD18
51DP_0P 30
RES3
45 RES24VDD11_L
52DP_0N 29 RES4
44 VDD185XI
53VDD11_DP 28 VDD11_FPD0
43 GPIO13 / SCK6XO
54DP_1P 27 DOUT0+
42 GPIO12 / SS7GPIO0
55DP_1N 26 DOUT0-
41 GPIO11 / MOSI8GPIO1
56VDD18_DP 25 VDD11_P
40 GPIO10 / MISO9GPIO2 / I2S_DC
57DP_2P 24 VDD18_FPD
39 GPIO910GPIO3 / I2S_DD
58DP_2N 23 DOUT1+
38 I2C_SDA211GPIO4 / REM_INTB
59VDD11_DP 22 DOUT1-
37 I2C_SCL212GPIO5 / I2S_DB
60DP_3P 21 VDD11_FPD1
36 I2C_SDA113GPIO6 / I2S_DA
61DP_3N 20 RBIAS
35 I2C_SCL114GPIO7 / I2S_WC
62DP_AUX_P 19 IDx
34 I2C_SDA015GPIO8 / I2S_CLK
63DP_AUX_N 18 MODE_SEL0
33 I2C_SCL016REFCLK1
64HPD 17 VDD11_P
Not to scale
DAP
TI Confidential — NDA Restrictions
5
DS90UB983-Q1
www.ti.com
SNLS606 –MARCH 2020
Product Folder Links: DS90UB983-Q1
Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated
6 Pin Configuration and Functions
Package
64-Pin QFN
Top View
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