jesd240-Xilinx FPGA实现

******************************************************************************* ** � Copyright 2006-2009, Xilinx, Inc. All rights reserved. ** This file contains confidential and proprietary information of Xilinx, Inc. and ** is protected under U.S. and international copyright and other intellectual property laws. ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ ** \ \ readme.txt Version: 1.0 ** / / Date Last Modified: Monday, September 14, 2009 ** /___/ /\ Date Created: Thursday, January 22, 2009 ** \ \ / \ Associated Filename: xapp876.zip ** \___\/\___\ ** ** Device: ** Purpose: Readme file for the JESD204A reference design. ** Reference: XAPP876.pdf ** Revision History: ** Rev. Monday 14 September 2009 ** Modified in all documents the LEAG HEADER information. ** Nothing else has been modified into the files included in the zip file of this design. ** All information in these zip files is identical to the ** "2-Lane_ADC_14Sep09_Xapp876.zip" file. ** ** For compatibility, compile, synthezise, or other reasons the filenames have not been ** changed. ** ******************************************************************************* ** ** Disclaimer: ** ** This disclaimer is not a license and does not grant any rights to the materials ** distributed herewith. Except as otherwise provided in a valid license issued to you ** by Xilinx, and to the maximum extent permitted by applicable law: ** (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, ** AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, ** INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR ** FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract ** or tort, including negligence, or under any other theory of liability) for any loss or damage ** of any kind or nature related to, arising under or in connection with these materials, ** including for any direct, or any indirect, special, incidental, or consequential loss ** or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered ** as a result of any action brought by a third party) even if such damage or loss was ** reasonably foreseeable or Xilinx had been advised of the possibility of the same. ** Critical Applications: ** ** Xilinx products are not designed or intended to be fail-safe, or for use in any application ** requiring fail-safe performance, such as life-support or safety devices or systems, ** Class III medical devices, nuclear facilities, applications related to the deployment of airbags, ** or any other applications that could lead to death, personal injury, or severe property or ** environmental damage (individually and collectively, "Critical Applications"). Customer assumes ** the sole risk and liability of any use of Xilinx products in Critical Applications, subject only ** to applicable laws and regulations governing limitations on product liability. ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ******************************************************************************* This readme describes how to use the files that come with XAPP876. ******************************************************************************* ** Directory structure ** <root> /2_lane_ADC_2008 /Documents This directory contains two pdf documents. One regarding the features used on the ML506 board for running the reference design and another showing a clock area on left and right side of the 'die' in a XC5VLX50T. Visio-Jesd204A_Ml505_Hardware_27Nov08.pdf Visio-Virtex-5_ClockArea_Left&RightDieSide.pdf /Ise /SysToplevel SysToplevel.ise Implementation of the reference design in ISE_10.1.03. The directory contains only the necessary files to get the ISE tool started. The implementation must be done at the users end. /SimScripts A set of .do files for use with Modelsim. The .do files called "xxxxx_FuncComp.do" are the files called for simulation compilation of the design. Those .dof files call the "xxxxx_FuncWave.do" files for showing of signals in the waveform window of Modelsim. Call the "xxxxx_FuncComp.do" file as follow: Start Modelsim (Modelsim SE6.4 was used to simulate the design)) In the main window select "Tools --> TCL --> Execute macro" Browse to the /SimScripts directory and select the .do file. Click "open". The design is compiled and synthesized for simulation and the "xxxxx_FuncWave.do" is called". In the Modelsim Transcipt winndow type: run <number of ticks> [enter]. The simulation waveform is displayed. /Simulation This is teh directory the simulator works in. All compiled and synthesized file results will end here. /Synthesis /Xst This is the directroy for implementation synthesis results. The design is synthezised with XST and only one directory (/Xst) with results is created. As you acn see in the propoerties of the XST tool in ISE Project manager the path for synthesis is set to this directory. When another synthesis tool is used, simly create a new subdirectory for that tool and use it for synthesis results. Example: When Synplicity is used, create a sub-directory /Synplicity Use that directory for storing the synthesis results. /Ucf Directory for User Constraints Files (UCF) Two files are available: The basic ML506 UCF file: Jesd204a_ML505.ucf The adapted ML506 UCF file: Jesd204a_ML505_03Sep08.ucf /Vhdl Source code storage. System Toplevel of the reference design and the ccompanying pdf document with block and schematic diagrams. SysToplevel.vhd Visio-SysToplevel.pdf /JesdAplication Source code files used for the application. /JesdToplevel Toplevel of the JESD204A interface. JesdToplevel.vhd Visio-JesdToplevel.pdf /JesdClk CMT-PLL implementation /JesdDscrmbl Descramble module /JesdGtp Dual GTP. /JesdMem Block-RAM memory data buffer /JesdSpiDrp Picoblaze controller of SPI, DRP and UART /Documents Files for compilation of Picoblaze code. /JesdStateMach /JesdKcharComp Comarision of K charecters. /JesdlaneAlign Chanel bonding /JesdLnkCnfg Storage in distributed memory of Link information /JesdSyncOut SYNC. *********************************************************************************************