FPGA 读写SDRAM 代码 SDRAM_TEST.RAR
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2014-10-04
10:21:19
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SDRAM_Test3.zip （70个子文件） 
SDRAM_Test 
PLL_ctrl.qip 542B rdfifo.v 7KB sdr_test.fit.summary 623B sdr_test.sof 235KB sdr_test.map.summary 481B PLL_ctrl_bb.v 13KB sdr_test.cdf 333B sdram_top.v 3KB sdr_test.pin 26KB sys_ctrl.v 2KB clk_ctrl.qip 456B uart_ctrl.v 1KB rdfifo.bsf 3KB stp1.stp 204KB sdr_para.v 3KB write_read.tbl 238KB sdr_test.v 5KB uart_speed_select.v 2KB uart_tx.v 2KB wrfifo_inst.v 188B PLL_ctrl.cnx 9KB sdr_test.fit.smsg 513B PLL_ctrl.ppf 614B wrfifo.qip 446B clk_ctrl.v 18KB sdr_test.qpf 907B rdfifo.qip 445B sdr_test.qsf 27KB clk_ctrl.ppf 617B rdfifo_inst.v 188B
wrfifo_waveforms.html 753B rdfifo_bb.v 6KB sdram_wr_data.v 3KB wrfifo.bsf 3KB PLL_ctrl_inst.v 162B PLL_ctrl.bsf 4KB sdr_test.done 26B wrfifo_bb.v 6KB sdram_cmd.v 5KB sdr_test.jdi 4KB sdr_test.sta.summary 4KB datagene.v 4KB clk_ctrl_inst.v 162B sdr_test.qws 532B PLL_ctrl.v 17KB clk_ctrl_bb.v 14KB 调式记录 
PLL_ctrl_wave0.jpg 782KB process2.jpg 123KB work_state_r.jpg 100KB wrfifo_wave0.jpg 96KB 1.jpg 441KB
rdack_2_9.bmp 1.91MB read_process.jpg 75KB sdr_test.jpg 101KB rdfifo_wave0.jpg 96KB process3.jpg 122KB rdack_0_7.bmp 1.91MB sdram_top_uut_sdramtop.jpg 71KB write_process.jpg 77KB process1.jpg 123KB init_state_r.jpg 70KB sdfifo_ctrl_uut_sdffifoctrl.jpg 51KB sdr_test_assignment_defaults.qdf 41KB PLL_ctrl_waveforms.html 862B rdfifo_waveforms.html 753B wrfifo.v 7KB PLL_ctrl.cnxerr 208B sdr_test.sdc 20KB sdfifo_ctrl.v 3KB sdram_ctrl.v 12KB资源评论
