SDRAM_test.zip_DSP FPGA sdram_FPGA DSP 接口_FPGA dsp_dsp fpga

#include <stdio.h> #include <csl.h> #include "reg6713.h" #define SDRAMWriteNum 16 #define SDRAMReadNum 16 #define SDRAMWriteBaseAddress0 0x080000000 #define SDRAMReadBaseAddress0 0x080000000 #define SDRAMWriteBaseAddress1 0x080100000 #define SDRAMReadBaseAddress1 0x080100000 #define SDRAMWriteBaseAddress2 0x080200000 #define SDRAMReadBaseAddress2 0x080200000 #define SDRAMWriteBaseAddress3 0x080300000 #define SDRAMReadBaseAddress3 0x080300000 #define SDRAMWriteBaseAddress4 0x081000000 /* this address range is not in SDRAM */ #define SDRAMReadBaseAddress4 0x081000000 void main() { int i; int *PSDRAM,SDRAMReadArray0[SDRAMReadNum],SDRAMReadArray1[SDRAMReadNum]; int SDRAMReadArray2[SDRAMReadNum],SDRAMReadArray3[SDRAMReadNum],SDRAMReadArray4[SDRAMReadNum]; //CSL_init(); /*-------------EMIF global Registers Configration-------*/ *(int *)EMIF_GCTL = 0x00003060;/* EMIF global control register */ *(int *)EMIF_CE1 = 0xFFFFFF23; /* CE1 - 16-bit asynch access */ *(int *)EMIF_CE0 = 0xFFFFFF30; /* CE0 - SDRAM */ *(int *)EMIF_CE2 = 0xFFFFFF23; /* CE2 - 32-bit asynch on daughterboard */ *(int *)EMIF_CE3 = 0xFFFFFF13; /* CE3 - 32-bit asynch on daughterboard */ *(int *)EMIF_SDRAMCTL = 0x57117000; /* SDRAM control register (100 MHz)*/ *(int *)EMIF_SDRAMTIMING = 0x0000061a; /* SDRAM Timing register */ /*------------- SDRAM write operation----------- */ for(i=0;i<SDRAMWriteNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress0+4*i); * PSDRAM=i; } for(i=0;i<SDRAMWriteNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress1+4*i); * PSDRAM=2*i; } for(i=0;i<SDRAMWriteNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress2+4*i); * PSDRAM=3*i; } for(i=0;i<SDRAMWriteNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress3+4*i); * PSDRAM=4*i; } for(i=0;i<SDRAMWriteNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress4+4*i); * PSDRAM=5*i; } /* ---------------SDRAM read operation -------------*/ for(i=0;i<SDRAMReadNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress0+4*i); SDRAMReadArray0[i]=* PSDRAM; } for(i=0;i<SDRAMReadNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress1+4*i); SDRAMReadArray1[i]=* PSDRAM; } for(i=0;i<SDRAMReadNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress2+4*i); SDRAMReadArray2[i]=* PSDRAM; } for(i=0;i<SDRAMReadNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress3+4*i); SDRAMReadArray3[i]=* PSDRAM; } for(i=0;i<SDRAMReadNum;i++) { PSDRAM=(int *)(SDRAMWriteBaseAddress4+4*i); SDRAMReadArray4[i]=* PSDRAM; } while(1); { asm(" nop 1"); } }