Book E:
Enhanced PowerPC Architecture
Version 1.0
May 7, 2002
ii Book E: Enhanced PowerPC Architecture Version 1.0 07 May 02
Third Edition (May 2002)
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The PowerPC Architecture: A Specification for a New Family of RISC Processors
, Second Edition (1994)
The IBM PowerPC Embedded Environment: Architectural Specifications for IBM PowerPC Embedded Controllers
,
Second Edition (1998)
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07 May 02 Preface iii
Preface
This release represents Version 1.0 of the Book E: Enhanced PowerPC Architecture.
07 May 02 Table of Contents v
Table of Contents
Chapter 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Compatibility with the PowerPC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 32-bit Book E Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Instruction Mnemonics and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.5 Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.5.1 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.5.2 Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5.3 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5.4 Reserved Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5.5 Preserved Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.6 Allocated Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.7 Description of Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Book E Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.7 Instruction Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7.1 Instruction Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.8 Classes of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.8.1 Defined Instruction Class. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.8.2 Allocated Instruction Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.8.3 Preserved Instruction Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.8.4 Reserved Instruction Class. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.9 Forms of Defined Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.9.1 Preferred Instruction Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.9.2 Invalid Instruction Forms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.10 Optionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.11 Storage Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.11.1 Storage Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.11.2 Effective Address Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.11.2.1 Data Storage Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.11.2.2 Instruction Storage Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . 32
1.11.3 Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.11.3.1 Structure Mapping Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.11.3.2 Instructions Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.11.3.3 Data Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.11.3.4 Integer Load and Store Byte-Reverse Instructions. . . . . . . . . . . . . . . . 36
1.11.3.5 Origin of Endian. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.12 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.12.1 Context Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.12.2 Execution Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 2. Processor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1 Processor Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1.1 Machine State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1.2 Processor Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.1.3 Processor Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.1.4 Software-Use Special Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.1.5 Device Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2 Processor Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2.1 System Linkage Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
