i
Version 2.02
PowerPC Operating Environment Architecture
Book III
Version 2.02
January 28, 2005
Manager:
Joe Wetzel/Poughkeepsie/IBM
Technical Content:
Ed Silha/Austin/IBM Cathy May/Watson/IBM Brad Frey/Austin/IBM
Junichi Furukawa/Austin/IBM Giles Frazier/Austin/IBM
Version 2.02
ii PowerPC Operating Environment Architecture
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Preface iii
Version 2.02
Preface
This document defines the additional instructions and
facilities, beyond those of the PowerPC User Instruc-
tion Set Architecture and PowerPC Virtual Environment
Architecture, that are provided by the PowerPC Operat-
ing Environment Architecture. It covers instructions
and facilities not available to the application program-
mer, affecting storage control, interrupts, and timing
facilities.
Other related documents define the PowerPCUser
Instruction Set Architecture, the PowerPC Virtual Envi-
ronment Architecture, and PowerPC Implementation
Features. Book I, PowerPC User Instruction Set Archi-
tecture defines the base instruction set and related
facilities available to the application programmer. Book
II, PowerPC Virtual Environment Architecture defines
the storage model and related instructions and facilities
available to the application programmer, and the Time
Base as seen by the application programmer. Book IV,
PowerPC Implementation Features defines the imple-
mentation-dependent aspects of a particular implemen-
tation.
As used in this document, the term “PowerPC Architec-
ture” refers to the instructions and facilities described in
Books I, II, and III. The description of the instantiation of
the PowerPC Architecture in a given implementation
includes also the material in Book IV for that implemen-
tation.
Note: Change bars indicate changes relative to Version
2.01.
Version 2.02
iv PowerPC Operating Environment Architecture
Table of Contents v
Version 2.02
Table of Contents
Chapter 1. Introduction . . . . . . . . . . 1
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Compatibility with the POWER Archi-
tecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Document Conventions . . . . . . . . . . 1
1.3.1 Definitions and Notation. . . . . . . . . 1
1.3.2 Reserved Fields. . . . . . . . . . . . . . . 2
1.4 General Systems Overview . . . . . . . 3
1.5 Exceptions . . . . . . . . . . . . . . . . . . . . 3
1.6 Synchronization . . . . . . . . . . . . . . . . 4
1.6.1 Context Synchronization . . . . . . . . 4
1.6.2 Execution Synchronization . . . . . . 4
1.7 Logical Partitioning (LPAR). . . . . . . . 5
1.7.1 Logical Partitioning Control Register
(LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7.2 Real Mode Offset Register (RMOR)6
1.7.3 Hypervisor Real Mode Offset Regis-
ter (HRMOR). . . . . . . . . . . . . . . . . . . . . . 6
1.7.4 Logical Partition
Identification Register (LPIDR) . . . . . . . . 7
1.7.5 Other Hypervisor Resources . . . . . 7
1.7.6 Sharing Hypervisor Resources . . . 8
Chapter 2. Branch Processor . . . . . 9
2.1 Branch Processor Overview . . . . . . . 9
2.2 Branch Processor Registers. . . . . . . 9
2.2.1 Machine Status Save/Restore Regis-
ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2 Hypervisor Machine Status Save/
Restore Registers . . . . . . . . . . . . . . . . . . 9
2.2.3 Machine State Register . . . . . . . . 10
2.3 Branch Processor Instructions . . . . 12
2.3.1 System Linkage Instructions . . . . 12
Chapter 3. Fixed-Point Processor 15
3.1 Fixed-Point Processor Overview . . 15
3.2 Special Purpose Registers . . . . . . . 15
3.3 Fixed-Point Processor Registers . . 15
3.3.1 Data Address Register. . . . . . . . . 15
3.3.2 Data Storage Interrupt
Status Register . . . . . . . . . . . . . . . . . . . 16
3.3.3 Software-use SPRs . . . . . . . . . . . 16
3.3.4 Control Register. . . . . . . . . . . . . . 17
3.3.5 Processor Version Register . . . . . 17
3.3.6 Processor Identification Register. 17
3.4 Fixed-Point Processor Instructions . 18
3.4.1 OR Instruction . . . . . . . . . . . . . . . 18
3.4.2 Move To/From System Register
Instructions . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 4. Storage Control . . . . . .25
4.1 Storage Addressing. . . . . . . . . . . . . 25
4.2 Storage Model . . . . . . . . . . . . . . . . 26
4.2.1 Storage Exceptions . . . . . . . . . . . 26
4.2.2 Instruction Fetch . . . . . . . . . . . . . 27
4.2.3 Data Access . . . . . . . . . . . . . . . . . 27
4.2.4 Performing Operations
Out-of-Order . . . . . . . . . . . . . . . . . . . . . 27
4.2.5 32-Bit Mode . . . . . . . . . . . . . . . . . 29
4.2.6 Real Addressing Mode. . . . . . . . . 29
4.2.7 Address Ranges Having Defined
Uses . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.8 Invalid Real Address . . . . . . . . . . 31
4.3 Address Translation Overview . . . . 32
4.4 Virtual Address Generation . . . . . . . 33
4.4.1 Segment Lookaside Buffer (SLB). 33
4.4.2 SLB Search . . . . . . . . . . . . . . . . . 34
4.5 Virtual to Real Translation . . . . . . . . 35
4.5.1 Page Table . . . . . . . . . . . . . . . . . . 36
4.5.2 Storage Description
Register 1 . . . . . . . . . . . . . . . . . . . . . . . 37
4.5.3 Page Table Search. . . . . . . . . . . . 38
4.6 Data Address Compare. . . . . . . . . . 39
4.7 Data Address Breakpoint . . . . . . . . 40
4.8 Storage Control Bits . . . . . . . . . . . . 41
4.8.1 Storage Control Bit Restrictions . . 42
4.8.2 Altering the Storage Control Bits . 42
4.9 Reference and Change Recording . 43
4.10 Storage Protection. . . . . . . . . . . . . 45
4.10.1 Storage Protection, Address Trans-
lation Enabled . . . . . . . . . . . . . . . . . . . . 45
4.10.2 Storage Protection, Address Trans-
lation Disabled . . . . . . . . . . . . . . . . . . . . 46
4.11 Storage Control Instructions . . . . . 47
4.11.1 Cache Management Instructions 47
4.11.2 Synchronize Instruction . . . . . . . 47
4.11.3 Lookaside Buffer
Management . . . . . . . . . . . . . . . . . . . . . 47
4.12 Page Table Update
Synchronization Requirements . . . . . . . 57
4.12.1 Page Table Updates. . . . . . . . . . 57
