SDRAM控制器(用Verilog编写）资源-CSDN文库

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asm：62个

dat：62个

vhd：62个

sdram

verilog

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SDRAM（Synchronous Dynamic Random-Access Memory）同步动态随机访问内存是一种常见的系统内存，它以时钟信号同步操作，提供高速数据传输。在 FPGA（Field-Programmable Gate Array）设计中，为了与SDRAM进行通信，需要一个专门的SDRAM控制器。本篇文章将详细介绍如何使用Verilog语言编写一个功能完善的SDRAM控制器。 Verilog是一种硬件描述语言，用于描述数字系统的逻辑行为，包括CPU、存储器控制器等。编写SDRAM控制器，主要涉及以下知识点： 1. **SDRAM时序**：理解SDRAM的时序是编写控制器的基础。这包括地址预充电、行激活、列选择、读写操作等。例如，控制器需要在正确的时间点发出命令，如RAS（行地址选通）、CAS（列地址选通）和CS（片选）信号。 2. **地址映射**：控制器需要将系统地址空间映射到SDRAM的物理地址上，处理地址线的分页和bank选择。 3. **刷新管理**：SDRAM需要定期刷新以保持数据的完整性，控制器需定时发送刷新命令。 4. **数据缓冲和同步**：由于SDRAM和FPGA内部逻辑速度不匹配，需要数据缓冲区进行同步，通常采用双口RAM实现。 5. **命令序列**：SDRAM的操作通常由一系列命令组成，如初始化、预充电、加载模式寄存器、读写等，控制器需要按照正确的顺序和时间间隔发出这些命令。 6. **时钟管理和DLL（Delay-Locked Loop）**：由于SDRAM时钟通常与系统时钟不同，控制器需要能够处理时钟域之间的转换。DLL用于调整时钟延迟，确保数据的准确同步。 7. **错误检测与处理**：控制器应包含错误检测机制，如读取数据的奇偶校验，以确保数据的正确性。 8. **仿真与验证**：在实际编写代码之前，通过行为模型进行仿真，验证控制器的功能和性能。使用工具如ModelSim或Vivado Simulator进行验证。 9. **综合与实现**：完成Verilog代码后，使用综合工具（如Synopsys的Design Compiler或Xilinx的Vivado）将其转换为逻辑门级网表，然后在FPGA上实现。 10. **硬件调试**：通过JTAG接口或其他调试工具进行硬件调试，检查SDRAM控制器的实际工作情况，确保其在真实环境中的正确运行。在"基于FPGA对SDRAM控制器的设计（VERILOG语言）"这个压缩包中，可能包含了详细的Verilog代码实现，以及相关的仿真波形、测试平台和文档说明，这些都是学习和理解SDRAM控制器设计的重要资源。通过分析和研究这些文件，可以深入理解上述知识点，并掌握实际的Verilog编程技巧。同时，这样的项目也提供了动手实践的机会，帮助提升FPGA设计能力。

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SDRAM控制器(用Verilog编写）（208个子文件）

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共 208 条

White Paper

SDR SDRAM Controller

August 2002, ver. 1.1 1

M-WP-SDR-1.1

Introduction

The single data rate (SDR) synchronous dynamic random access memory (SDRAM) controller provides a simplified

interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in either Verilog HDL or

VHDL and is optimized for the Altera

APEX

™

architecture. The SDR SDRAM Controller supports the following

features:

■ Burst lengths of 1, 2, 4, or 8 data words

■ CAS latency of 2 or 3 clock cycles

■ 16-bit programmable refresh counter used for automatic refresh

■ 2-chip selects for SDRAM devices

■ Supports the NOP, READA, WRITEA, AUTO_REFRESH, PRECHARGE, ACTIVATE, BURST_STOP,

and LOAD_MR commands

■ Support for full-page mode operation

■ Data mask line for write operations

■ PLL to increase system performance

■ Support for data-path widths of 16, 32, and 64 bits

Figure 1 shows a system-level diagram of the SDR SDRAM Controller.

Figure 1. SDR SDRAM Controller System-Level Diagram

SDRAM Overview

SDRAM is high-speed dynamic random access memory (DRAM) with a synchronous interface. The synchronous

interface and fully-pipelined internal architecture of SDRAM allows extremely fast data rates if used efficiently.

Internally, SDRAM devices are organized in banks of memory, which are addressed by row and column. The number

of row- and column-address bits and the number of banks depends on the size of the memory.

SDR SDRAM

Controller

SDR SDRAM

CLK

CS_N

CKE

CAS_N

WE_N

DQM

RAS_N

CLK

CMD[1:0]

CMDACK

ADDR

DATAIN

DATAOUT

Altera Corporation SDR SDRAM Controller White Paper

SDRAM is controlled by bus commands that are formed using combinations of the RASN, CASN, and WEN signals.

For instance, on a clock cycle where all three signals are high, the associated command is a no operation (NOP). A

NOP is also indicated when the chip select is not asserted. Table 1 shows the standard SDRAM bus commands.

SDRAM banks must be opened before a range of addresses can be written to or read from. The row and bank to be

opened are registered coincident with the ACT command. When a bank is accessed for a read or a write it may be

necessary to close the bank and re-open it if the row to be accessed is different than the row that is currently opened.

Closing a bank is done with the PCH command.

The primary commands used to access SDRAM are RD and WR. When the WR command is issued, the initial col-

umn address and data word is registered. When a RD command is issued, the initial address is registered. The initial

data appears on the data bus 1 to 3 clock cycles later. This is known as CAS latency and is due to the time required to

physically read the internal DRAM core and register the data on the bus. The CAS latency depends on the speed of

the SDRAM and the frequency of the memory clock. In general, the faster the clock, the more cycles of CAS latency

are required. After the initial RD or WR command, sequential read and writes continue until the burst length is

reached or a BT command is issued. SDRAM memory devices support burst lengths of 1, 2, 4, or 8 data cycles. The

ARF is issued periodically to ensure data retention. This function is performed by the SDR SDRAM Controller and is

transparent to the user.

The LMR is used to configure the SDRAM mode register. which stores the CAS latency, burst length, burst type, and

write burst mode. Consult the SDRAM specification for additional details.

SDRAM comes in dual in-line memory modules (DIMMs), small-outline DIMMs (SO-DIMMs) and chips. To reduce

pin count SDRAM row and column addresses are multiplexed on the same pins. SDRAM often includes more than

one bank of memory internally and DIMMS may require multiple chip selects.

Table 1. SDRAM Bus Commands

Command Abbreviation RASN CASN WEN

No operation NOP H H H

Active ACT L H H

Read RD H L H

Write WR H L L

Burst terminate BT H H L

Precharge PCH L H L

Autorefresh ARF L L H

Load mode register LMR L L L

Altera Corporation SDR SDRAM Controller White Paper

Functional Description

Table 2 shows the SDR SDRAM Controller interface signals. All signals are synchronous to the system clock and

outputs are registered at the SDR SDRAM Controller’s outputs.

Table 2. Interface Signals

Signal Name Active I/O Description

CLK Clock NA Input System clock.

RESET_N Reset Low Input System reset.

ADDR[ASIZE-1:0] Memory address NA Input Memory address for read/write requests. Width is set by

ASIZE.

CMD[2:0] Command NA Input Command request.

CMDACK Command acknowledge High Output Acknowledgment of the requested command.

DATAIN[DSIZE-1:0] Input data NA Input Input data bus. Width is set by DSIZE.

DATAOUT[DSIZE-1:0] Output data NA Output Output data bus. Width is set by DSIZE.

DM[(DSIZE/8)-1:0] Data mask High Input Masks individual bytes during data write

SA[11:0] Address bus NA Output SA[11:0] are sampled during the ACT command to latch

the row address. SA[n:0] are sampled during the RD/WR

command to latch the column address where n depends on

the size of SDRAM used. SA[10] is sampled during the

PCH command to determine if all banks are to be pre-

charged or the bank selected by BA[1:0]. The address out-

puts also provide the op-code during the LMR command.

BA[1:0] Bank address NA Output These signals determine to which bank the ACT, RD, WR, or

PCH command is applied.

CS_N[1:0] Chip selects Low Output SDRAM chip selects.

CKE Clock enable High Output SDRAM CKE input.

RAS_N Row address strobe Low Output SDRAM command input.

CAS_N Column address strobe Low Output SDRAM command input.

WE_N Write enable Low Output SDRAM command input.

DQ[DSIZE-1:0] Data bus NA I/O SDRAM data bus.

DQM[(DSIZE/8)-1:0] Data mask High Output SDRAM data masks, mask individual bytes during data

write.

Altera Corporation SDR SDRAM Controller White Paper

SDRAM Controller Command Interface

The SDR SDRAM Controller provides a synchronous command interface to the SDRAM and several control regis-

ters. Table 3 shows the commands, which are described in following sections. The following rules apply to the com-

mands:

■ All commands, except NOP, are driven by the user onto CMD[2:0]; ADDR and DATAIN are set appropri-

ately for the requested command. The controller registers the command on the next rising clock edge

■ To acknowledge the command the controller asserts CMDACK for one clock period

■ For READA or WRITEA commands, the user should start receiving or writing data on DATAOUT and

DATAIN

■ The user must drive NOP onto CMD[2:0]by the next rising clock edge after CMDACK is asserted

NOP Command

NOP is a no operation command to the controller. When NOP is detected by the controller, it performs a NOP in the

following clock cycle. A NOP must be issued the following clock cycle after the controller has acknowledged a com-

mand. The NOP command has no affect on SDRAM accesses that are already in progress.

READA Command

The READA command instructs the SDR SDRAM Controller to perform a burst read with auto-precharge to the

SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller issues an ACTIVATE command

to the SDRAM followed by a READA command. The read burst data first appears on DATAOUT (RCD + CL + 2)

after the SDR SDRAM Controller asserts CMDACK. During a READA command the user must keep DM low. When

the controller is configured for full-page mode, the READA command becomes READ (READ without auto-pre-

charge). Figure 2 shows an example timing diagram for a READA command. The following sequence describes the

general operation of the READA command:

■ The user asserts READA, ADDR and DM

■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu-

ing commands to the SDRAM devices

■ One clock after CMDACK is asserted, the user must assert NOP

■ The CMDACK presents the first read burst value on DATAOUT, the remainder of the read bursts follow every

clock cycle

Table 3. Interface Commands

Command Value Description

NOP 000b No operation.

READA 001b SDRAM read with auto precharge.

WRITEA 010b SDRAM write with auto precharge.

REFRESH 011b SDRAM auto refresh.

PRECHARGE 100b SDRAM precharge all banks.

LOAD_MODE 101b SDRAM load mode register.

LOAD_REG1 110b Load controller configuration register.

LOAD_REG2 111b Load controller refresh period register.

Altera Corporation SDR SDRAM Controller White Paper

Figure 2. READA Timing Diagram

WRITEA Command

The WRITEA command instructs the SDR SDRAM Controller to perform a burst write with auto-precharge to the

SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller will issue an ACTIVATE com-

mand to the SDRAM followed by a WRITEA command. The first data value in the burst sequence must be presented

with the WRITEA and ADDR address. The host must start clocking data along with the desired DM values into the

SDR SDRAM Controller (t

RCD

– 2) clocks after the SDR SDRAM Controller has acknowledged the WRITEA com-

mand. See a SDRAM data sheet for how to use the data mask lines DM/DQM.

When the SDR SDRAM Controller is in the full-page mode WRITEA becomes WRITE (write without auto-pre-

charge). Figure 3 shows an example timing diagram for a WRITEA command. The following sequence describes the

general operation of a WRITEA command:

■ The user asserts WRITEA, ADDR, the first write data value on DATAIN, and the desired data mask value on

■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu-

ing commands to the SDRAM devices

■ One clock after CMDACK was asserted, the user asserts NOP on CMD

■ The user clocks data and data mask values into the SDR SDRAM Controller through DATAIN and DM

Address

1234...n-6n-5n-4

Row

Column

CLK

CMD

CMDACK

ADDR

DATAOUT

DQM

RAS_N

CAS_N

WE_N

CS_N

CKE

NOP

READA

1 2 ... n-8 n-7 n-6 n-5 n-4

NOP

D.C.

D.C. = Don't Care

D.C.

PRECHARGE NOP

nn-1n-2n-3

n-1n-2n-3

评论收藏

内容反馈

星河无涯

2014-05-26

他说很不错。
zlq999

2014-02-28

建议加入一些控制器参数设定方面的资料，看起来很吃力，我用的64M好像还对不起来，现在还没用起来。
zhuimeng0001

2014-10-31

很有帮助，不错
Happy_Traveller

2013-07-01

对初学者，还是挺有价值的！
yuanwei19900815

2013-12-03

代码很清楚，对初学者蛮有用的

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