Advanced_Digital_Design_with_the_Verilog_HDL源码
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2010-11-20
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Advanced_Digital_Design_with_the_Verilog_HDL源码 （947个子文件） 
ADDVB_Models_9.doc 267KB ADDVB_Models_9.doc 267KB ADDVB_Models_10.doc 224KB ADDVB_Models_10.doc 224KB ADDVB_Models_5.doc 167KB ADDVB_Models_5.doc 167KB ADDVB_Models_7.doc 161KB ADDVB_Models_7.doc 161KB ADDVB_Models_11.doc 140KB ADDVB_Models_11.doc 140KB ADDVB_Models_6.doc 118KB ADDVB_Models_6.doc 118KB ADDVB_Models_8.doc 105KB ADDVB_Models_8.doc 105KB ADDVB_Models_4.doc 73KB ADDVB_Models_4.doc 73KB Gap_Finder.doc 34KB Gap_Finder.doc 34KB FAQs.doc 23KB Uni_dir_bus.v.doc 19KB Uni_dir_bus.v.doc 19KB ADDVB_Models_4.doc 634B Uni_dir_bus.v.doc 588B Uni_dir_bus.v.doc 588B ADDVB_Models_10.doc 507B ADDVB_Models_10.doc 507B ADDVB_Models_11.doc 491B ADDVB_Models_9.doc 461B ADDVB_Models_9.doc 461B ADDVB_Models_6.doc 453B ADDVB_Models_6.doc 453B ADDVB_Models_7.doc 453B ADDVB_Models_7.doc 453B ADDVB_Models_8.doc 421B ADDVB_Models_8.doc 421B ADDVB_Models_5.doc 405B ADDVB_Models_5.doc 405B ADDVB_Models_4.doc 634B ADDVB_Models_11.doc 491B
ADDVB_Models_7.v.txt 30KB ADDVB_Models_7.v.txt 30KB README.txt 957B README.txt 957B compare_2_CA1.txt 267B compare_2_CA1.txt 267B compare_2_CA1.txt 257B compare_2_CA1.txt 257B
Image_converter_2.v 17KB Image_converter_2.v 17KB RISC_SPM.v 14KB RISC_SPM.v 14KB SRAM_with_Con.v 11KB SRAM_with_Con.v 11KB Radix_4__STG_0.v 10KB Radix_4__STG_0.v 10KB RAM_2048_8.v 10KB RAM_2048_8.v 10KB t_ASIC_with_TAP.v 8KB t_ASIC_with_TAP.v 8KB Image_Converter_1.v 8KB Image_Converter_1.v 8KB Image_Converter_0.v 7KB Image_Converter_0.v 7KB Multiplier_Implicit_2.v 7KB Multiplier_Implicit_2.v 7KB Divider_STG_1.v 6KB Divider_STG_1.v 6KB Multiplier_Booth_STG_0.v 6KB Multiplier_Booth_STG_0.v 6KB Image_Converter_Baseline.v 6KB Image_Converter_Baseline.v 6KB Multiplier_Implicit_1.v 6KB Multiplier_Implicit_1.v 6KB uart8_rcvr_partition.v 6KB uart8_rcvr_partition.v 6KB t_Image_Converter_1.v 5KB t_Image_Converter_2.v 5KB t_Image_Converter_1.v 5KB t_Image_Converter_2.v 5KB Divider_RR_STG.v 5KB Divider_RR_STG.v 5KB t_Image_Converter_Baseline.v 5KB t_Image_Converter_Baseline.v 5KB t_Image_Converter_0.v 5KB t_Image_Converter_0.v 5KB uart8_rcvr.v 5KB uart8_rcvr.v 5KB UART_xmtr_Arch.v 4KB UART_xmtr_Arch.v 4KB Multiplier_STG_1.v 4KB Multiplier_STG_1.v 4KB Divider_STG_0.v 4KB Divider_STG_0.v 4KB Divider_STG_0_sub.v 4KB Divider_STG_0_sub.v 4KB Multiplier_STG_0.v 4KB Multiplier_STG_0.v 4KB ASIC_with_BIST.v 4KB ASIC_with_BIST.v 4KB Seq_Rec_3_1s.v 3KB共 947 条
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