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Introduction to Verilog
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Course Objectives
n Learn the basic constructs of Verilog
n Learn the modeling structure of Verilog
n Learn the concept of delays and their effects in
simulation
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Course Outline
n Verilog Overview
n Basic Structure of a Verilog Model
n Components of a Verilog Module
– Ports
– Data Types
– Assigning Values and Numbers
– Operators
– Behavioral Modeling
• Continuous Assignments
• Procedural Blocks
– Structural Modeling
n Summary: Verilog Environment
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Verilog
Overview
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What is Verilog?
n IEEE industry standard Hardware Description
Language (HDL) - used to describe a digital system
n For both Simulation & Synthesis
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