LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TIMES IS
PORT(CLR:IN STD_LOGIC;
CLK:IN STD_LOGIC;
ENA:IN STD_LOGIC;
DISPLAY:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SEG_SEL:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY TIMES;
ARCHITECTURE ART OF TIMES IS
COMPONENT CLKGEN IS
PORT(CLK:IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC);
END COMPONENT CLKGEN;
COMPONENT CNT10 IS
PORT(CLK,CLR,ENA:IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT:OUT STD_LOGIC);
END COMPONENT CNT10;
COMPONENT CNT6 IS
PORT(CLK,CLR,ENA:IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT:OUT STD_LOGIC);
END COMPONENT CNT6;
SIGNAL S0:STD_LOGIC;
SIGNAL S1,S2,S3,S4,S5:STD_LOGIC;
SIGNAL DISP_TEMP :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DISP_DECODE :STD_LOGIC_VECTOR(7 DOWNTO 0);
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