官方原版资料 RH850 Family 32 User’s Manual: Software Renesas microcontroller RH850 Family
CHAPTER 1 OVERVIEW ...............................................................................................................1
1.1 V850E3v5 Architecture Features ...........................................................................................1
1.1.1 Multi-processing environment .....................................................................................2
1.1.2 Virtual machines...........................................................................................................2
1.1.3 Hardware multithreading..............................................................................................2
1.2 V850E3v5 Architecture Class ................................................................................................3
1.3 Changes from the V850E2v3 Architecture ............................................................................4
CHAPTER 2 PROCESSOR MODEL ................................................................................................5
2.1 Resource Management ...........................................................................................................5
(1) 3-layer control system..................................................................................................6
(2) 2-layer control system..................................................................................................7
2.2 CPU Operating Modes............................................................................................................8
2.2.1 Definition of CPU operating modes.............................................................................9
(1) Native mode (NM).......................................................................................................9
(2) Virtual machine mode (VM) .......................................................................................9
(3) Supervisor mode (SV) .................................................................................................9
(4) User mode (UM)..........................................................................................................9
2.2.2 CPU operating mode transition .................................................................................... 10
(1) Change due to acknowledging an exception ...............................................................10
(2) Change due to a return instruction...............................................................................10
(3) Change due to a system register instruction................................................................10
2.2.3 CPU operating modes and privileges...........................................................................11
(1) Hypervisor privilege (HV privilege) ...........................................................................12
(2) Supervisor privilege (SV privilege).............................................................................12
(3) Coprocessor use permissions.......................................................................................12
(4) Operation when there is a privilege violation .............................................................13
2.3 Hardware Thread ....................................................................................................................14
2.3.1 Thread status.................................................................................................................14
(1) Enabled/disabled..........................................................................................................14
(2) Stopped/running...........................................................................................................14
2.3.2 Stopping a thread by executing the HALT instruction ................................................15
2.3.3 Pausing a thread by executing the SNOOZE instruction.............................................15
2.4 Instruction Execution..............................................................................................................16
2.5 Exceptions and Interrupts .......................................................................................................17
2.5.1 Types of exceptions......................................................................................................17
(1) Terminating exceptions ...............................................................................................17
(2) Resumable exceptions .................................................................................................17
(3) Pending exceptions ......................................................................................................17
2.5.2 Exception level ................................................................................................................18
2.6 Coprocessors..............................................................................................................................18
2.6.1 Coprocessor use permissions...........................................................................................18
2.6.2 Correspondences between coprocessor use permissions and coprocessors ...................19
2.6.3 Coprocessor unusable exceptions....................................................................................19
2.6.4 System registers...............................................................................................................19
2.7 Registers.....................................................................................................................................20
2.7.1 Program registers.............................................................................................................20
2.7.2 System registers...............................................................................................................20
2.7.3 Register updating.............................................................................................................22
(1) LDSR and STSR..........................................................................................................22
(2) LDTC and STTC .........................................................................................................25
