没有合适的资源?快使用搜索试试~ 我知道了~
EDA考试模块.pdf
1.该资源内容由用户上传,如若侵权请联系客服进行举报
2.虚拟产品一经售出概不退款(资源遇到问题,请及时私信上传者)
2.虚拟产品一经售出概不退款(资源遇到问题,请及时私信上传者)
版权申诉
0 下载量 130 浏览量
2023-06-19
13:19:40
上传
评论 1
收藏 309KB PDF 举报
温馨提示
试读
24页
EDA考试模块.pdf
资源推荐
资源详情
资源评论
文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.
全加器
--full_adder1
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(Ai,Bi,Ci_1: in std_logic;
Ci,Si: out std_logic);
end full_adder;
architecture full_adder_arch of full_adder is
begin
Si<=Ai xor Bi xor Ci_1;
Ci<=((Ai or Bi)and Ci_1) or (Ai and Bi);
end full_adder_arch;
--full_adder2
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(Ai,Bi,Ci_1: in std_logic;
Ci,Si: out std_logic);
end full_adder;
architecture full_adder_arch of full_adder is
signal ABC:std_logic_vector(2 downto 0);
signal Y: std_logic_vector(1 downto 0);
begin
ABC<=Ai&Bi&Ci_1;
with ABC select
Y<="00" when "000",
"10" when "001",
"10" when "010",
"01" when "011",
"10" when "100",
"01" when "101",
"01" when "110",
"11" when others;
Si<=Y(1);
Ci<=Y(0);
end full_adder_arch;
--full_adder3
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
1文档来源为:从网络收集整理.word 版本可编辑.
文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.
port(Ai,Bi,Ci_1: in std_logic;
Ci,Si: out std_logic);
end full_adder;
architecture full_adder_arch of full_adder is
signal ABC:std_logic_vector(2 downto 0);
signal Y: std_logic_vector(1 downto 0);
begin
ABC<=Ai&Bi&Ci_1;
Y<="00" when ABC="000" else
"10" when ABC="001" else
"10" when ABC="010" else
"01" when ABC="011" else
"10" when ABC="100" else
"01" when ABC="101" else
"01" when ABC="110" else
"11" ;
Si<=Y(1);
Ci<=Y(0);
end full_adder_arch;
--full_adder4
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(Ai,Bi,Ci_1: in std_logic;
Ci,Si: out std_logic);
end full_adder;
architecture full_adder_arch of full_adder is
signal ABC:std_logic_vector(2 downto 0);
signal Y: std_logic_vector(1 downto 0);
begin
ABC<=Ai&Bi&Ci_1;
process(ABC,Ai,Bi,Ci_1)
begin
If ABC="000" then Y<="00";
elsif ABC="001" then Y<="10";
elsif ABC="010" then Y<="10";
elsif ABC="011" then Y<="01";
elsif ABC="100" then Y<="10";
elsif ABC="101" then Y<="01";
elsif ABC="110" then Y<="01";
else Y<="11";
end if;
Si<=Y(1);
Ci<=Y(0);
2文档来源为:从网络收集整理.word 版本可编辑.
文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.
end process;
end full_adder_arch;
--full_adder5
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(Ai,Bi,Ci_1: in std_logic;
Ci,Si: out std_logic);
end full_adder;
architecture full_adder_arch of full_adder is
signal ABC:std_logic_vector(2 downto 0);
signal Y: std_logic_vector(1 downto 0);
begin
ABC<=Ai&Bi&Ci_1;
process(ABC,Ai,Bi,Ci_1)
begin
case ABC is
when"000"=>Y<="00";
when"001"=>Y<="10";
when"010"=>Y<="10";
when"011"=>Y<="01";
when"100"=>Y<="10";
when"101"=>Y<="01";
when"110"=>Y<="01";
when"111"=>Y<="11";
end case;
Si<=Y(1);
Ci<=Y(0);
end process;
end full_adder_arch;
D 锁存器
library ieee;
use ieee.std_logic_1164.all;
entity dff1 is
port(D,clk: in std_logic;
Q: buffer std_logic);
end dff1;
architecture behave of dff1 is
begin
process(clk,Q)
begin
3文档来源为:从网络收集整理.word 版本可编辑.
文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.
if clk'event and clk='1' then Q<=D;
end if;
end process;
end behave;
JK 触发器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity JK_chufa is
Port ( sd,rd,j,k,clk:in std_logic;
q,qb: out std_logic
);
end JK_chufa;
architecture behave of JK_chufa is
signal qn:std_logic;
begin
process(clk)
begin
if sd='0' and rd='1' then qn<='1';
elsif sd='1' and rd='0' then qn<='0';
elsif sd='1' and rd='1' then
if rising_edge(clk) then
qn<=(j and not qn) or(not k and qn);
end if;
end if;
end process;
q<=qn;
qb<=not qn;
end behave;
10 进制计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity module_10 is
port(ep,et,clr,load,clk: in std_logic;
d: in std_logic_vector(3 downto 0);
co: out std_logic;
q: buffer std_logic_vector(3 downto 0)
);
end module_10;
4文档来源为:从网络收集整理.word 版本可编辑.
文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.
architecture behave of module_10 is
begin
co<='1' when(q="1001" and ep='1' and et='1') else
'0';
process(clk,clr)
begin
if (clr='0') then q<="0000";
elsif rising_edge(clk) then
if load='0' then q<=d;
elsif (ep='1' and et='1') then
if(q=9) then q<="0000";
else q<=q+1;
end if;
end if;
end if;
end process;
end behave;
扫描显示
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CNT8 IS
PORT(CLK:IN STD_LOGIC;
Q:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0));
END;
ARCHITECTURE BEH OF CNT8 IS
BEGIN
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
IF Q=7 THEN Q<="000";
ELSE Q<=Q+1;END IF;
END IF;
END PROCESS;
END;
library ieee;
use ieee.std_logic_1164.all;
entity dec7s is
port(a:in std_logic_vector(2 downto 0);
led7s:out std_logic_vector(6 downto 0));
5文档来源为:从网络收集整理.word 版本可编辑.
剩余23页未读,继续阅读
资源评论
hhappy0123456789
- 粉丝: 61
- 资源: 5万+
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- 1961ee27df03bd4595d28e24b00dde4e_744c805f7e4fb4d40fa3f695bfbab035_8(1).c
- mediapipe-0.9.0.1-cp37-cp37m-win-amd64.whl.zip
- windows注册表编辑工具
- mediapipe-0.9.0.1-cp37-cp37m-win-amd64.whl.zip
- 校园通行码预约管理系统20240522075502
- 车类型数据集6250张VOC+YOLO格式.zip
- The PyTorch implementation of STGCN.STGCN-main.zip
- 092300108.cpp
- 车类型数据集6000张VOC+YOLO格式.zip
- for daily read
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功