LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS -- 顶层设计
PORT ( --CLK12MHZ : IN STD_LOGIC; --端口说明语句
--CLK8HZ : IN STD_LOGIC;
CLK50MHZ : IN STD_LOGIC;
CODE1 : OUT INTEGER RANGE 0 TO 15;
HIGH1,SPKOUT : OUT STD_LOGIC);
END;
ARCHITECTURE one OF TOP IS
COMPONENT Tone ------------说明语句
PORT ( Index : IN INTEGER RANGE 0 TO 15;
CODE : OUT INTEGER RANGE 0 TO 15;
HIGH : OUT STD_LOGIC;
Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); --11位2进制数
END COMPONENT;
COMPONENT Speaker
PORT ( clk : IN STD_LOGIC;
Tone1 : IN INTEGER RANGE 0 TO 16#7FF#; --11位2进制数
SpkS : OUT STD_LOGIC );
END COMPONENT;
component Notetabs
Port ( clk :in std_logic;
index0 : out INTEGER RANGE 0 TO 15);
end component;
COMPONENT clkdiv8Hz
PORT ( clk : IN STD_LOGIC;
clk_out8Hz : OUT STD_LOGIC );
END COMPONENT;
COMPONENT clkdiv12MHz
PORT ( clk : IN STD_LOGIC;
clk_out12MHz : OUT STD_LOGIC );
END COMPONENT;
SIGNAL Tone2 : INTEGER RANGE 0 TO 16#7FF#;
SIGNAL Indx: INTEGER RANGE 0 TO 15;
SIGNAL CLK8HZ: STD_LOGIC ;
SIGNAL CLK12MHZ: STD_LOGIC ;
BEGIN -- 安装U1, U2, U3
u1 : Tone PORT MAP (Index=>Indx, Tone=>Tone2,CODE=>CODE1,HIGH=>HIGH1);------功能描述雨语句
u2 : Speaker PORT MAP (clk=>CLK12MHZ,Tone1=>Tone2, SpkS=>SPKOUT );
u3 : Notetabs PORT MAP(clk=>CLK8HZ,Index0=>Indx);
U4 : clkdiv8Hz PORT MAP(CLK=>CLK50MHZ,clk_out8Hz=>CLK8HZ);
U5 : clkdiv12MHz PORT MAP(CLK=>CLK50MHZ,clk_out12MHz=>CLK12MHZ);
END;
-------2-----为Speaker提供决定所发音符的分频预置数，而此数在Speaker输入口停留的时间即为此音符的节拍值
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Tone IS
PORT ( Index : IN INTEGER RANGE 0 TO 15;
CODE : OUT INTEGER RANGE 0 TO 15;
HIGH : OUT STD_LOGIC;
Tone : OUT INTEGER RANGE 0 TO 16#7FF# );
END;
ARCHITECTURE one OF Tone IS
