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Application Note
DA1453x Hardware Guidelines
AN-B-075
Abstract
This Application Note provides the minimal reference schematic, circuit explanation, and design
guidelines for BLE applications based on the DA1453x SoCs.
AN-B-075
DA1453x Hardware Guidelines
Application Note
Revision 1.8
01-Dec-2022
CFR0014
2 of 48
© 2022 Renesas Electronics
Contents
Abstract ................................................................................................................................................ 1
Contents ............................................................................................................................................... 2
Figures .................................................................................................................................................. 3
Tables ................................................................................................................................................... 4
1 Terms and Definitions ................................................................................................................... 5
2 References ..................................................................................................................................... 6
3 Introduction.................................................................................................................................... 7
3.1 Device Revision Numbering and Marking ............................................................................. 9
3.2 The DA14531 System ......................................................................................................... 10
3.2.1 The Power Section of DA14531 .......................................................................... 10
3.2.1.1 The PMU of DA14531...................................................................... 10
3.2.1.2 Important Notices for PMU .............................................................. 13
3.2.1.3 Supplying External Loads ................................................................ 14
3.2.1.4 The Passive Components ............................................................... 14
3.2.2 XTAL, 32 MHz (Y1) .............................................................................................. 21
3.2.2.1 32 MHz XTAL Trimming .................................................................. 22
3.2.2.2 Improved XTAL32M setting ............................................................. 23
3.2.3 XTAL, 32.768 kHz (Y2) ........................................................................................ 24
3.2.4 Reset.................................................................................................................... 25
3.2.5 JTAG .................................................................................................................... 25
3.2.6 UART ................................................................................................................... 26
3.2.7 SPI Data Flash ..................................................................................................... 26
3.3 RF Section .......................................................................................................................... 27
3.3.1 Pi Filter ................................................................................................................. 28
3.3.2 Conducted Performance ...................................................................................... 29
3.3.2.1 TX Measurements ........................................................................... 29
3.3.2.2 RX Measurements ........................................................................... 29
3.3.3 Antenna and Current Measurements .................................................................. 29
4 PCB Layout Guidelines ............................................................................................................... 30
4.1 PCB Layout of DA14531-00FXDB-P/ DA14531-01FXDB-P (FCGQFN24) ........................ 30
4.1.1 Minimal System PCB Layout for FCQFN24 ........................................................ 34
4.2 PCB Layout of DA14531-0 OGDB-P PRO-Devkit (WLCSP) .............................................. 35
4.2.1 PCB Layout Guidelines........................................................................................ 36
4.2.2 Minimal System PCB Layout for WLCSP17 ........................................................ 39
Appendix A Special considerations for Reset Functionality ........................................................ 40
A.1 Reset Pad (P0_0) ................................................................................................................ 40
A.2 Booting Sequence and P0_0 .............................................................................................. 41
A.3 SPI FLASH .......................................................................................................................... 42
A.4 Examples ............................................................................................................................ 43
A.4.1 Example 1: Booting from 2-wire UART ................................................................ 43
A.4.2 Example 2: RST/P0_0 signal shared with FLASH .............................................. 43
Appendix B External filtering for Quadrature Decoder ................................................................. 45
Revision History ................................................................................................................................ 47
AN-B-075
DA1453x Hardware Guidelines
Application Note
Revision 1.8
01-Dec-2022
CFR0014
3 of 48
© 2022 Renesas Electronics
Figures
Figure 1: DA14531 Block Diagram ........................................................................................................ 8
Figure 2: WLCSP17 Ball Assignment (Top View) ................................................................................. 8
Figure 3: FCGQFN24 Pin Assignment (Top View) ............................................................................... 8
Figure 4: DA14531 FCGQFN24 Package Marking ............................................................................... 9
Figure 5: DA14531 WLCSP17 Package Marking ................................................................................. 9
Figure 6: DA14531 System Configurations ......................................................................................... 10
Figure 7: DA14531 SoC power management unit (PMU) ................................................................... 11
Figure 8: Battery Connection for Buck (Left), Boost (Middle) or Bypass (Right) Configuration .......... 11
Figure 9: Maximum DC Load on VBAT_HIGH rail during boot ........................................................... 13
Figure 10: Examples of SPI Flash power management using (a) analog switch (b) GPIO ................ 13
Figure 11: Effective Capacitance of a 2.2 μF Ceramic Capacitor ....................................................... 15
Figure 12: df2 Performance Versus C2 Value in Boost Mode ............................................................ 15
Figure 13: Buck Configuration ............................................................................................................. 16
Figure 14: Boost Configuration ............................................................................................................ 16
Figure 15: Bypass Configuration ......................................................................................................... 16
Figure 16: DA14531 DCDC Power Efficiency. DCDC is Configured in BUCK Mode ......................... 19
Figure 17: DA14531 DCDC Power Efficiency. Boost Mode, Produced Voltage VBAT_HIgh=3V ...... 19
Figure 18: DA14531 DCDC Power Efficiency. Boost Mode, produced voltage VBAT_HIgh=2.5V .... 20
Figure 19: DA14531 DCDC Power Efficiency. Boost Mode, Produced Voltage VBAT_HIgh=1.8V ... 20
Figure 20: The Circuit of 32 MHz Crystal Oscillator ............................................................................ 22
Figure 21: 32 MHz XTAL Oscillator Capacitance Value Versus Frequency ....................................... 23
Figure 22: Debugger Enabling ............................................................................................................ 25
Figure 23: Single UART Hardware Configuration ............................................................................... 26
Figure 24: SPI Data Flash Hardware Setup ........................................................................................ 27
Figure 25: DA14531 RF Section ......................................................................................................... 27
Figure 26: Pi Filter Topology ............................................................................................................... 28
Figure 27. S21 Simulated Parameters ................................................................................................ 28
Figure 28: DA14531 FCGQFN24 Reference Circuit ........................................................................... 30
Figure 29: PCB Cross Section ............................................................................................................ 31
Figure 30: PCB Placement and Routing – Top Layer ......................................................................... 32
Figure 31: FCGQFN24 PCB Placement and Routing – GND Plane - INT1 Layer.............................. 32
Figure 32: FCGQFN24 PCB Placement and Routing – INT2 Layer ................................................... 33
Figure 33: FCGQFN24 PCB Placement and Routing – GND Bottom Layer ...................................... 33
Figure 34: PCB Occupied Area for DA14531-FCGQFN24 System, ................................................... 34
Figure 35: DA14531 WLCSP17 Reference Circuit ............................................................................. 35
Figure 36: PCB Cross Section ............................................................................................................ 35
Figure 37: WLCSP17 - PCB Placement and Routing – Top Layer ..................................................... 37
Figure 38: WLCSP17 PCB Placement and Routing – GND plane - INT1 Layer ................................ 37
Figure 39: WLCSP17 PCB Placement and Routing - INT2 Layer ...................................................... 38
Figure 40: WLCSP17 PCB Placement and Routing – Bottom Layer .................................................. 38
Figure 41: PCB Occupied Area for DA14531-WLCSP17 System....................................................... 39
Figure 42: Type B GPIO Pad-GPIO with Schmitt Trigger & RC filter .................................................. 40
Figure 43: Reset Block Diagram ......................................................................................................... 41
Figure 44: Booting sequence and booting pins for DA14531 .............................................................. 41
Figure 45: P0_0 connected to SPI_MOSI ........................................................................................... 42
Figure 46: FTDI and DA14531 connection circuit for Reset ................................................................ 43
Figure 47: Example of Connecting a Sensor to the SPI BUS and an MCU to RST and UART of
DA14531 SmartBond TINY™ Module [376-23-B] ............................................................................... 44
Figure 48: Quadrature decoder block diagram.................................................................................... 45
Figure 49: Suggested filter for mechanical incremental encoder ........................................................ 46
AN-B-075
DA1453x Hardware Guidelines
Application Note
Revision 1.8
01-Dec-2022
CFR0014
4 of 48
© 2022 Renesas Electronics
Tables
Table 1: Ordering Information ............................................................................................................... 8
Table 2: CHIP_REVISION_REG (0x50003214).................................................................................... 9
Table 3: CHIP_TEST1_REG (0x500032F8) ......................................................................................... 9
Table 4: Chip Revision Numbering ........................................................................................................ 9
Table 5: Typical Rail Voltages and their Sources in the Various PMU Modes ................................... 12
Table 6: DA14531 DCDC External Load Supply Capability ................................................................ 14
Table 7: DFE2016E-2R2M Characteristics ......................................................................................... 17
Table 8: Tested Inductors on DA14531 PRO-Devkit .......................................................................... 18
Table 9: Inductor Peak Current Limit ................................................................................................... 21
Table 10: XTAL32 MHz Oscillator - Recommended Operating Conditions ........................................ 21
Table 11: Successfully Tested Crystals .............................................................................................. 22
Table 12: Selected Main XTAL Specification ...................................................................................... 22
Table 13: XTAL Oscillator 32kHz - Recommended Operating Conditions ......................................... 24
Table 14: Selected Main XTAL Specification ...................................................................................... 24
Table 15: P0_0 Assignment During Boot ............................................................................................ 25
Table 16: DA14531 Pins Assignment for SPI Data Slave on Booting ................................................ 26
Table 17: Fundamental Power and Harmonics, Conducted Mode, PA in 3 dBm Mode ..................... 29
Table 18: LO Leakage, Conducted Mode Results .............................................................................. 29
Table 19: P0_0 Assignment During Boot ............................................................................................ 42
AN-B-075
DA1453x Hardware Guidelines
Application Note
Revision 1.8
01-Dec-2022
CFR0014
5 of 48
© 2022 Renesas Electronics
1 Terms and Definitions
BLE Bluetooth
®
Low Energy
IC Integrated Circuit
SoC System on Chip
RF Radio Frequency
PMU Power Management Unit
SRAM Static Random-Access Memory
OTP One Time Programmable
UART Universal Asynchronous Receiver Transmitter
GPIO General Purpose Input Output (pin)
ILIM DCDC Inductor peak current limit
JTAG Joint Test Action Group
SWD Serial Wire Debug
SPI Serial Peripheral Interface
CS Chip Select
SDK Software Development Kit
PRO-Devkit DA14531 PRO Development kit
PCB Printed Circuit Board
PCBA Printed Circuit Board Assembly
BOM Bill Of Materials
DCR DC Resistance
PTH Plated Through Hole
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