Cyclone2 FPGA读写SRAM IS61LV25616 实验Verilog逻辑源码Quartus工程文件.zip

Cyclone2 FPGA读写SRAM IS61LV25616 实验Verilog逻辑源码Quartus工程文件 module SRAM_TEST ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output inout [15:0] SRAM_DQ , output reg [17:0] SRAM_ADDR , output reg SRAM_CE , output reg SRAM_OE , output reg SRAM_WE , output reg SRAM_UB , output reg SRAM_LB , output reg [ 7:0] LED ); //Reg define reg [3:0] div_cnt ; reg sram_clk ; reg [5:0] ctrl_cnt ; reg [15:0] sram_data_lck ; reg [15:0] sram_din ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to sram ctrl clk 50M/16 always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 4'b0; else div_cnt <= div_cnt + 4'b1; end //gen sram_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) sram_clk <= 1'b0 ; else if ( div_cnt <= 4'd7 ) sram_clk <= 1'b1 ; else sram_clk <= 1'b0 ; end // sram ctrl signal gen // ctrl_cnt 0 - 31 is for write ctrl // ctrl_cnt 31 - 63 is for read ctrl always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 6'b0; else ctrl_cnt <= ctrl_cnt + 6'b1; end always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) SRAM_ADDR <= 18'b0; else if ( ctrl_cnt