iv
3.5.1. Discovery without CE_n pin reduction ..................................................................... 76
3.5.2. Discovery with CE_n pin reduction .......................................................................... 77
3.5.3. Target Initialization ................................................................................................... 80
4. Data Interface and Timing ...................................................................................................... 81
4.1. Data Interface Type Overview ........................................................................................ 81
4.2. Signal Function Assignment............................................................................................ 82
4.3. Bus State ......................................................................................................................... 82
4.3.1. SDR.......................................................................................................................... 83
4.3.2. NV-DDR ................................................................................................................... 83
4.3.3. NV-DDR2 and NV-DDR3 ......................................................................................... 84
4.3.4. Pausing Data Input/Output ...................................................................................... 84
4.4. NV-DDR / NV-DDR2 / NV-DDR3 and Repeat Bytes ...................................................... 85
4.5. Data Interface / Timing Mode Transitions ....................................................................... 85
4.5.1. SDR Transition from NV-DDR or NV-DDR2 ............................................................ 86
4.5.2. NV-DDR2 Recommendations .................................................................................. 86
4.5.3. NV-DDR3 Recommendations .................................................................................. 86
4.6. Test Conditions ............................................................................................................... 87
4.6.1. SDR Only ................................................................................................................. 87
4.6.2. Devices that Support Driver Strength Settings ........................................................ 87
4.7. ZQ Calibration ................................................................................................................. 88
4.7.1. ZQ External Resistor Value, Tolerance, and Capacitive loading ............................ 89
4.8. I/O Drive Strength ........................................................................................................... 89
4.9. Output Slew Rate ............................................................................................................ 90
4.10. Capacitance ................................................................................................................. 95
4.10.1. Legacy Capacitance Requirements ..................................................................... 95
4.10.2. Capacitance Requirements (Informative)............................................................. 97
4.10.3. Package Electrical Specifications and Pad Capacitance ..................................... 99
4.11. Impedance Values ..................................................................................................... 100
4.11.1. NV-DDR ............................................................................................................. 101
4.11.2. NV-DDR2 ........................................................................................................... 103
4.11.3. NV-DDR3 ........................................................................................................... 105
4.12. Output Driver Sensitivity ............................................................................................ 107
4.13. Input Slew Rate Derating .......................................................................................... 108
4.13.1. NV-DDR ............................................................................................................. 108
4.13.2. NV-DDR2/NV-DDR3 .......................................................................................... 108
4.14. Differential Signaling (NV-DDR2/NV-DDR3) ............................................................. 114
4.15. Warmup Cycles (NV-DDR2/NV-DDR3) ..................................................................... 115
4.16. On-die Termination (NV-DDR2/NV-DDR3) ............................................................... 115
4.16.1. ODT Sensitivity ................................................................................................... 118
4.16.2. Self-termination ODT.......................................................................................... 119
4.16.3. Matrix Termination .............................................................................................. 120
4.17. Timing Parameters .................................................................................................... 127
4.17.1. General Parameters ........................................................................................... 128
4.17.2. SDR .................................................................................................................... 130
4.17.3. NV-DDR ............................................................................................................. 131
4.17.4. NV-DDR2/NV-DDR3 .......................................................................................... 132
4.18. Timing Modes ............................................................................................................ 133
4.18.1. SDR .................................................................................................................... 133
4.18.2. NV-DDR ............................................................................................................. 135
4.18.3. NV-DDR2/NV-DDR3 .......................................................................................... 138
4.19. Timing Diagrams ....................................................................................................... 143
4.19.1. SDR .................................................................................................................... 143
4.19.2. NV-DDR ............................................................................................................. 151
4.19.3. NV-DDR2 and NV-DDR3 ................................................................................... 162
5. Command Definition ............................................................................................................. 168
5.1. Command Set ............................................................................................................... 168
