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74HC20 pdf

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两组四输入与非门。 The 74HC20; 74HCT20 is a dual 4-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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1. General description

The 74HC20; 74HCT20 is a dual 4-input NAND gate. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of

2. Features and benefits

 Complies with JEDEC standard JESD7A

 Low-power dissipation

 Input levels:

 For 74HC20: CMOS level

 For 74HCT20: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 Cto+80C and from 40 Cto+125C.

3. Ordering information

74HC20; 74HCT20

Dual 4-input NAND gate

Rev. 3 — 3 September 2012 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC20N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT20N

74HC20D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT20D

74HC20DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm

SOT337-1

74HCT20DB

74HC20PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT20PW

Product data sheet Rev. 3 — 3 September 2012 2 of 16

NXP Semiconductors

74HC20; 74HCT20

Dual 4-input NAND gate

4. Functional diagram

5. Pinning information

5.1 Pinning

Fig 1. Functional diagram Fig 2. Logic symbol

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Fig 3. IEC Logic symbol Fig 4. Logic diagram

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Fig 5. Pin configuration SOT27-1 and SOT108-1 Fig 6. Pin configuration SOT337-1 and SOT402-1

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Product data sheet Rev. 3 — 3 September 2012 3 of 16

NXP Semiconductors

74HC20; 74HCT20

Dual 4-input NAND gate

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP14 package: P

tot

derates linearly with 12 mW/K above 70 C.

For SO14 package: P

tot

derates linearly with 8 mW/K above 70 C.

For (T)SSOP14 packages: P

tot

derates linearly with 5.5 mW/K above 60 C.

Table 2. Pin description

Symbol Pin Description

1A, 1B, 1C, 1D 1, 2, 4, 5 data input

n.c. 3, 11 not connected

1Y 6 data output

GND 7 ground (0 V)

2Y 8 data output

2A, 2B, 2C, 2D 9, 10, 12, 13 data input

14 supply voltage

Table 3. Function table

[1]

Input Output

nA nB nC nD nY

LXXXH

XLXXH

XXLXH

XXXLH

HHHHL

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

supply voltage 0.5 +7 V

input clamping current V

< 0.5 V or V

+0.5 V

[1]

- 20 mA

output clamping current V

< 0.5 V or V

+0.5V

[1]

- 20 mA

output current 0.5 V < V

< V

+0.5V - 25 mA

supply current - 50 mA

GND

ground current 50 - mA

stg

storage temperature 65 +150 C

tot

total power dissipation

[2]

DIP14 package - 750 mW

SO14, and (T)SSOP14

packages

- 500 mW

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