// synthesis verilog_input_version verilog_2001
`timescale 1 ps / 1 ps
module altpcierd_dprambe (wrclk, wraddr, wrdata, wrbe, rdclk, rdclken,
rdaddr, rddata);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 32;
parameter BYTE_SIZE = 8;
input wrclk;
input[ADDR_WIDTH - 1:0] wraddr;
input[DATA_WIDTH - 1:0] wrdata;
input[DATA_WIDTH / BYTE_SIZE - 1:0] wrbe;
input rdclk;
input rdclken;
input[ADDR_WIDTH - 1:0] rdaddr;
output[DATA_WIDTH - 1:0] rddata;
wire[DATA_WIDTH - 1:0] rddata;
wire [DATA_WIDTH - 1:0] q_a;
wire wren;
assign wren = 1'b1 ;
altsyncram dpram(
.wren_a(wren),
.clock0(wrclk),
.clock1(rdclk),
.clocken1(rdclken),
.byteena_a(wrbe),
.address_a(wraddr),
.address_b(rdaddr),
.data_a(wrdata),
.q_b(rddata),
.q_a(q_a),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_b(1'b1),
.aclr0(1'b0),
.aclr1(1'b0),
.clocken0(1'b1),
.data_b({DATA_WIDTH{1'b1}}),
.rden_b(1'b1),
.wren_b(1'b0)
);
defparam
dpram.operation_mode = "DUAL_PORT",
dpram.width_a = DATA_WIDTH,
dpram.widthad_a = ADDR_WIDTH,
dpram.numwords_a = (1<<ADDR_WIDTH),
dpram.width_b = DATA_WIDTH,
dpram.widthad_b = ADDR_WIDTH,
dpram.numwords_b = (1<<ADDR_WIDTH),
dpram.lpm_type = "altsyncram",
dpram.width_byteena_a = DATA_WIDTH/BYTE_SIZE,
dpram.outdata_reg_b = "CLOCK1",
dpram.indata_aclr_a = "NONE",
dpram.wrcontrol_aclr_a = "NONE",
dpram.address_aclr_a = "NONE",
dpram.byteena_aclr_a = "NONE",
dpram.address_reg_b = "CLOCK1",
dpram.address_aclr_b = "NONE",
dpram.outdata_aclr_b = "NONE",
dpram.ram_block_type = "AUTO",
dpram.intended_device_family = "Stratix";
endmodule
