ofdm交织编码的Verilog实现_verilog交织资源-CSDN文库

共39个文件

v：5个

sym：4个

xco：4个

Verilog

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data_interleaver_ise10migration.zip （39个子文件）

rcount_1.vho 3KB

dint_ram2.sym 1KB

dint_ram.vhd 5KB

count24.edn 17KB

data_interleaver.ise_ISE_Backup 288KB

count24.veo 3KB

rcount_1.v 4KB

dint_ram2.v 4KB

dint_ram.edn 20KB

rcount_1.xco 2KB

_xmsgs

count24.asy 424B

data_interleaver_xdb

tmp

dint_ram.xco 2KB

data_interleaver.v 7KB

dint_ram2.veo 3KB

data_interleaver.ise 288KB

dint_ram2.xco 2KB

count24.sym 687B

rcount_1.veo 3KB

dint_ram2.mif 96B

dint_ram2.edn 13KB

rcount_1.asy 451B

dint_ram.veo 3KB

dint_ram.v 5KB

count24.v 4KB

dint_ram.asy 910B

rcount_1.edn 26KB

data_interleaver.restore 48KB

rcount_1.vhd 4KB

dint_ram2.vhd 5KB

dint_ram2.vho 4KB

count24.vho 3KB

count24.xco 2KB

templates

coregen.xml 5KB

count24.vhd 4KB

rcount_1.sym 686B

data_interleaver_summary.html 2KB

dint_ram2.asy 907B

dint_ram.vho 4KB

dint_ram.sym 1KB

<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD COLSPAN='4'>DATA_INTERLEAVER Project Status</TD></TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'>Project File:</TD> <TD>data_interleaver.ise</TD> <TD BGCOLOR='#FFFF99'>Current State:</TD> <TD>New</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'>Module Name:</TD> <TD>data_interleaver</TD> <TD BGCOLOR='#FFFF99'><UL><LI>Errors:</LI></UL></TD> <TD> </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'>Target Device:</TD> <TD>xc3s500e-4fg320</TD> <TD BGCOLOR='#FFFF99'><UL><LI>Warnings:</LI></UL></TD> <TD> </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'>Product Version:</TD> <TD>ISE 9.2i</TD> <TD BGCOLOR='#FFFF99'><UL><LI>Updated:</LI></UL></TD> <TD>??? ?? 16 19:35:55 2008</TD> </TR> </TABLE>   <TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'>DATA_INTERLEAVER Partition Summary</TD></TR> <TR><TD COLSPAN='4'>No partition information was found.</TD></TR> </TABLE>   <TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'>Detailed Reports</TD></TR> <TR BGCOLOR='#FFFF99'><TD>Report Name</TD><TD>Status</TD><TD>Generated</TD> <TD ALIGN=LEFT>Errors</TD><TD ALIGN=LEFT>Warnings</TD><TD ALIGN=LEFT>Infos</TD></TR> <TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD></TR> <TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD></TR> <TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD></TR> <TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD></TR> <TR ALIGN=LEFT><TD>Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD></TR> <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD></TR> </TABLE> </BODY></HTML>

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