+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; ROM_inst|altsyncram_component|auto_generated ; 13 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ROM_inst ; 13 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
FPGA Verilog DDS 雏形，本资源只是为了调用一下rom ip核 具体使用流程看说明 （162个子文件） 
_info 1KB _vmake 26B DDS.root_partition.cmp.ammdb 666B DDS.vpr.ammdb 664B DDS.map.ammdb 129B sin_wave_4096x8.mif.bak 49KB DDS.vt.bak 3KB DDS_run_msim_rtl_verilog.do.bak 612B DDS.v.bak 448B DDS_run_msim_rtl_verilog.do.bak1 612B DDS.cmp.bpm 811B DDS.map.bpm 773B DDS.cmp.cdb 12KB DDS.root_partition.cmp.cdb 6KB DDS.rtlv_sg.cdb 6KB DDS.map.cdb 5KB DDS.root_partition.map.cdb 4KB DDS.sgdiff.cdb 4KB DDS.(0).cnf.cdb 2KB DDS.map_bb.cdb 2KB DDS.(1).cnf.cdb 2KB DDS.rtlv_sg_swap.cdb 2KB DDS.(3).cnf.cdb 2KB DDS.(2).cnf.cdb 1KB DDS.root_partition.map.hbdb.cdb 1KB DDS.root_partition.map.reg_db.cdb 217B logic_util_heursitic.dat 5KB _primary.dat 2KB _primary.dat 495B _primary.dat 439B DDS_8_1200mv_85c_board_slow.data 5KB DDS_board.data 5KB DDS_8_1200mv_0c_board_slow.data 5KB DDS_min_1200mv_0c_board_fast.data 4KB DDS_8_slow_1200mv_0c.data 4KB DDS_8_slow_1200mv_85c.data 4KB DDS_MIN_fast_1200mv_0c.data 4KB DDS.db_info 140B DDS.db_info 140B _primary.dbs 1KB _primary.dbs 675B _primary.dbs 529B DDS.tiscmp.slow_1200mv_85c.ddb 121KB DDS.tiscmp.slow_1200mv_0c.ddb 121KB DDS.tiscmp.fast_1200mv_0c.ddb 120KB DDS.tiscmp.fastest_slow_1200mv_85c.ddb 105KB DDS.tiscmp.fastest_slow_1200mv_0c.ddb 105KB DDS.asm_labs.ddb 17KB DDS.tis_db_list.ddb 310B DDS.pti_db_list.ddb 246B DDS.root_partition.cmp.dfp 33B DDS_run_msim_rtl_verilog.do 612B DDS.done 26B DDS.root_partition.map.dpi 2KB DDS.root_partition.map.hbdb.hb_info 46B DDS.pre_map.hdb 15KB DDS.rtlv.hdb 14KB DDS.cmp.hdb 14KB DDS.root_partition.cmp.hdb 14KB DDS.sgdiff.hdb 14KB DDS.map.hdb 13KB DDS.root_partition.map.hdb 13KB DDS.root_partition.map.hbdb.hdb 13KB DDS.map_bb.hdb 11KB DDS.(1).cnf.hdb 1KB DDS.(0).cnf.hdb 1KB DDS.(2).cnf.hdb 853B DDS.(3).cnf.hdb 753B DDS.hier_info 9KB DDS.hif 2KB DDS.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd 729KB DDS.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd 727KB DDS.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd 723KB
DDS.lpc.html 816B DDS.cmp.idb 2KB modelsim.ini 11KB DDS.ipinfo 369B DDS.jdi 222B DDS.root_partition.map.kpt 638B DDS.map.kpt 635B DDS.cmp_merge.kpt 206B .cmp.kpt 201B DDS.cmp.logdb 16KB DDS.root_partition.cmp.logdb 4B DDS.map.logdb 4B DDS.map_bb.logdb 4B sin_wave_4096x8.mif 1023B sin_wave_4096x8.mif 1023B DDS_board.mod 3KB DDS_8_1200mv_85c_board_slow.mod 3KB DDS_min_1200mv_0c_board_fast.mod 3KB DDS_8_1200mv_0c_board_slow.mod 3KB DDS_MIN_fast_1200mv_0c.mod 2KB DDS_8_slow_1200mv_0c.mod 2KB DDS_8_slow_1200mv_85c.mod 2KB msim_transcript 2KB DDS.pin 32KB verilog.prw 2KB verilog.prw 435B verilog.prw 289B共 162 条
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