FPGA+Altera收发器PHYIP内核用户指南资源-CSDN文库

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Altera 收发器 PHY IP 内核用户指南

内容

Protocol-Specific 和 Native Transceiver PHY 的介绍.......................................1-1

Protocol-Specific Transceiver PHY...........................................................................................................1-1

Native Transceiver PHY............................................................................................................................. 1-2

Non-Protocol-Specific Transceiver PHY................................................................................................. 1-4

收发器 PHY 模块........................................................................................................................................1-4

收发器重配置控制器.................................................................................................................................1-5

复位收发器 PHY.........................................................................................................................................1-5

运行仿真测试台..........................................................................................................................................1-6

不支持的特性：..........................................................................................................................................1-8

入门指南概述...................................................................................................... 2-1

IP 内核的安装和授权................................................................................................................................2-1

设计流程.......................................................................................................................................................2-2

MegaWizard Plug-In Manager 流程........................................................................................................ 2-3

指定参数...........................................................................................................................................2-3

仿真 IP 内核.....................................................................................................................................2-4

10GBASE-R PHY IP 内核...................................................................................3-1

10GBASE-R PHY 发布信息...................................................................................................................... 3-6

10GBASE-R PHY 器件系列支持..............................................................................................................3-6

Stratix IV 器件的 10GBASE-R PHY 性能和资源利用.........................................................................3-7

Arria V GT 器件的 10GBASE-R PHY 性能和资源使用......................................................................3-7

Arria V GZ 和 Stratix V 器件的 10GBASE-R PHY 性能和资源使用............................................... 3-7

参数化 10GBASE-R PHY...........................................................................................................................3-8

常用选项参数..............................................................................................................................................3-8

Stratix IV 器件的模拟参数..................................................................................................................... 3-11

10GBASE-R PHY 接口.............................................................................................................................3-12

10GBASE-R PHY 数据接口....................................................................................................................3-13

10GBASE-R PHY 状态，1588 和 PLL 参考时钟接口.......................................................................3-16

可选复位控制和状态接口......................................................................................................................3-17

Arria V GT 器件的 10GBASE-R PHY 时钟......................................................................................... 3-18

Arria V GZ 器件的 10GBASE-R PHY 时钟......................................................................................... 3-18

Stratix IV 器件的 10GBASE-R PHY 时钟.............................................................................................3-19

Stratix V 器件的 10GBASE-R PHY 时钟..............................................................................................3-20

10GBASE-R PHY 寄存器接口和寄存器的描述.................................................................................3-21

Stratix IV 器件的 10GBASE-R PHY 动态重配置............................................................................... 3-26

Arria V 和 Stratix V 器件的 10GBASE-R PHY 动态重配置.............................................................3-26

1588 延迟要求...........................................................................................................................................3-27

10GBASE-R PHY TimeQuest 时序约束............................................................................................... 3-27

10GBASE-R PHY 仿真文件和实例测试台..........................................................................................3-29

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具有早期访问 FEC 选项的 10GBASE-KR PHY IP 内核...................................4-1

10GBASE-KR PHY 发布信息................................................................................................................... 4-2

器件系列支持..............................................................................................................................................4-2

10GBASE-KR PHY 性能和资源使用......................................................................................................4-3

参数化 10GBASE-KR PHY........................................................................................................................4-3

10GBASE-KR 链路训练参数 .......................................................................................................4-4

10GBASE-KR 自动协商参数........................................................................................................4-5

10GBASE-R 参数.............................................................................................................................4-6

1GbE 参数.........................................................................................................................................4-7

速度检测参数..................................................................................................................................4-8

PHY 模拟参数.................................................................................................................................4-8

10GBASE-KR PHY IP 内核功能描述......................................................................................................4-9

10GBASE-KR PHY 仲裁逻辑要求........................................................................................................ 4-13

10GBASE-KR PHY 状态机逻辑要求....................................................................................................4-14

前向纠错(Clause 74).................................................................................................................................4-14

10BASE-KR PHY 接口.............................................................................................................................4-18

10GBASE-KR PHY 时钟和复位接口....................................................................................................4-19

10GBASE-KR PHY 数据接口..................................................................................................... 4-20

10GBASE-KR PHY 控制和状态接口........................................................................................4-23

菊花链接口信号............................................................................................................................4-25

嵌入式处理器接口信号.............................................................................................................. 4-26

动态重新配置接口信号.............................................................................................................. 4-27

寄存器接口信号........................................................................................................................................4-28

10GBASE-KR PHY 寄存器定义.............................................................................................................4-29

PMA 寄存器...............................................................................................................................................4-42

PCS 寄存器.................................................................................................................................................4-43

PMA 寄存器...............................................................................................................................................4-43

创建 10GBASE-KR 设计..........................................................................................................................4-44

编辑一个 10GBASE-KR MIF 文件 ....................................................................................................... 4-45

设计实例.....................................................................................................................................................4-46

SDC 时序约束........................................................................................................................................... 4-47

缩略语.........................................................................................................................................................4-47

1G/10 Gbps Ethernet PHY IP 内核.....................................................................5-1

1G/10GbE PHY 发布信息......................................................................................................................... 5-2

器件系列支持..............................................................................................................................................5-3

10GBASE-KR PHY 性能和资源使用......................................................................................................5-3

参数化 1G/10GbE PHY..............................................................................................................................5-4

1GbE 参数.....................................................................................................................................................5-4

速度检测参数..............................................................................................................................................5-5

PHY 模拟参数.............................................................................................................................................5-6

1G/10GbE PHY 接口..................................................................................................................................5-7

1G/10GbE PHY 时钟和复位接口............................................................................................................5-8

1G/10GbE PHY 数据接口......................................................................................................................... 5-9

XGMII 映射到标准 SDR XGMII 数据................................................................................................. 5-10

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串行数据接口............................................................................................................................................5-12

1G/10GbE 控制和状态接口....................................................................................................................5-12

寄存器接口信号........................................................................................................................................5-13

1G/10GbE PHY 寄存器定义...................................................................................................................5-14

PMA 寄存器...............................................................................................................................................5-15

PCS 寄存器.................................................................................................................................................5-16

10GBASE-KR GMII PCS 寄存器............................................................................................................5-16

PMA 寄存器...............................................................................................................................................5-18

从 1G 到 10GbE 的 1G/10GbE 动态重配置.........................................................................................5-19

1G/10GbE PHY 仲裁逻辑要求.............................................................................................................. 5-20

1G/10GbE PHY 状态机逻辑要求..........................................................................................................5-21

编辑 1G/10GbE MIF 文件 ......................................................................................................................5-21

创建 1G/10GbE 设计................................................................................................................................5-22

动态重新配置接口信号.......................................................................................................................... 5-23

1G/10 Gbps Ethernet PHY IP 内核........................................................................................................ 5-24

设计实例.....................................................................................................................................................5-25

仿真支持.....................................................................................................................................................5-26

TimeQuest 时序约束................................................................................................................................5-27

缩略语.........................................................................................................................................................5-27

XAUI PHY IP 内核..............................................................................................6-1

XAUI PHY 版本信息..................................................................................................................................6-1

XAUI PHY 器件系列支持.........................................................................................................................6-2

Stratix IV 器件 XAUI PHY 的性能和资源利用率 .............................................................................. 6-3

Arria V GZ 和 Stratix V 器件 XAUI PHY 的性能和资源利用率......................................................6-3

参数化 XAUI PHY......................................................................................................................................6-3

XAUI PHY General 参数........................................................................................................................... 6-4

XAUI PHY 模拟参数..................................................................................................................................6-6

Arria II GX、Arria II GZ、HardCopy IV 和 Stratix IV 器件的 XAUI PHY 模拟参数.................6-6

Advanced Options 参数............................................................................................................................. 6-7

XAUI PHY 配置.......................................................................................................................................... 6-8

XAUI PHY 端口.......................................................................................................................................... 6-9

XAUI PHY 数据接口............................................................................................................................... 6-11

SDR XGMII TX 接口....................................................................................................................6-12

SDR XGMII RX 接口....................................................................................................................6-13

收发器串行数据接口...................................................................................................................6-13

XAUI PHY 时钟、复位和断电接口.....................................................................................................6-13

XAUI PHY PMA 通道控制器接口........................................................................................................6-15

XAUI PHY 可选 PMA 控制和状态接口..............................................................................................6-15

XAUI PHY 寄存器接口和寄存器说明.................................................................................................6-18

Arria II GX、Cyclone IV GX、HardCopy IV GX 和 Stratix IV GX 的 XAUI PHY 动态重配

置 ...........................................................................................................................................................6-24

Arria V、Arria V GZ、Cyclone V 和 Stratix V 器件的 XAUI PHY 动态重配置........................ 6-24

逻辑通道分配限制.......................................................................................................................6-25

XAUI PHY 动态重配置接口信号..............................................................................................6-25

SDC 时序约束........................................................................................................................................... 6-26

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仿真文件和实例测试平台......................................................................................................................6-26

Interlaken PHY IP 内核......................................................................................7-1

Interlaken PHY 器件系列支持.................................................................................................................7-2

参数化 Interlaken PHY.............................................................................................................................. 7-2

Interlaken PHY 可选的端口参数.............................................................................................................7-3

Interlaken PHY 通用参数..........................................................................................................................7-3

Interlaken PHY 模拟参数..........................................................................................................................7-5

Interlaken PHY 接口...................................................................................................................................7-6

Interlaken PHY Avalon-ST TX 接口........................................................................................................7-6

Interlaken PHY Avalon-ST RX 接口........................................................................................................7-9

Interlaken PHY TX 和 RX 串行接口.....................................................................................................7-12

Interlaken PHY PLL 接口........................................................................................................................ 7-13

去偏移的 Interlaken 可选时钟...............................................................................................................7-13

Interlaken PHY 寄存器接口和寄存器说明.........................................................................................7-14

为什么收发器动态重配置......................................................................................................................7-17

动态收发器重配置接口.......................................................................................................................... 7-18

Interlaken PHY TimeQuest 时序约束...................................................................................................7-18

Interlaken PHY 仿真文件和实例测试台..............................................................................................7-18

PHY IP Core for PCI Express (PIPE) .................................................................8-1

PHY for PCIe (PIPE)器件系列支持.........................................................................................................8-3

PHY for PCIe (PIPE) 资源利用................................................................................................................ 8-3

参数化 PHY IP Core for PCI Express (PIPE)......................................................................................... 8-3

PHY for PCIe (PIPE)一般选项参数.........................................................................................................8-3

PHY for PCIe (PIPE)接口..........................................................................................................................8-5

来自 PHY MAC 的 PHY for PCIe (PIPE)输入数据............................................................................. 8-6

到 PHY MAC 的 PHY for PCIe (PIPE)输出数据................................................................................8-10

PHY for PCIe (PIPE)时钟........................................................................................................................8-12

Gen3 设计的 PHY for PCIe (PIPE)时钟 SDC 时序约束...................................................................8-13

PHY for PCIe (PIPE)可选状态接口...................................................................................................... 8-13

PHY for PCIe (PIPE)串行数据接口...................................................................................................... 8-14

PHY for PCIe (PIPE)寄存器接口和寄存器说明.................................................................................8-14

Gen3 数据速率的 PHY for PCIe (PIPE)链路均衡..............................................................................8-20

阶段 0.............................................................................................................................................. 8-21

阶段 1.............................................................................................................................................. 8-21

阶段 2(可选的)..............................................................................................................................8-21

阶段 3(可选的)..............................................................................................................................8-22

调整链路伙伴的发送器的建议................................................................................................. 8-22

使能 PCIe Gen3 的动态 PMA 调整.......................................................................................................8-22

PHY for PCIe (PIPE)动态重配置...........................................................................................................8-22

逻辑通道分配限制.......................................................................................................................8-23

PHY for PCIe (PIPE)仿真文件和实例测试台.....................................................................................8-24

自定义 PHY IP 内核........................................................................................... 9-1

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